• Silicon System Level Test

    NVIDIA (Santa Clara, CA)
    …challenges across diverse industries. NVIDIA's Silicon Solutions Group (SSG) seeks a Test Development Engineer to join our Hardware Architecture ... and system Product of Record (POR) alignment. As a Test Prototyping Engineer , you will create new...stand out from the crowd: + Experience in rack-level test development Our team is at the… more
    NVIDIA (01/22/25)
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  • Product Engineer , Tessent/Design…

    Siemens (Fremont, CA)
    …IC packaging + DFT and test for embedded IP cores + Failure diagnosis + ATE use / test program development + Candidate should be high energy, curious ... seeks a highly motivated, creative, and energetic individual as Product Engineer , specializing in design-for- test (DFT) and test delivery at chip and system… more
    Siemens (03/04/25)
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  • Field Application Engineer (SEG, San Jose…

    Teradyne (San Jose, CA)
    Test /Product engineering experience in analog, digital, mixed signal or RF testing and test development on ATE (Automated Test Equipment) platforms + ... looking for a highly-motivated, energetic and driven Field Application Engineer , who will work collaboratively with the team as...solutions for Analog and Mixed Signal semiconductor devices. + Test program software development , often done in… more
    Teradyne (02/20/25)
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  • DFT Engineer

    Broadcom (San Jose, CA)
    …Verifying & Debugging Test vectors before tape release. + Validating & Debugging Test vectors on ATE during the silicon bring up phase + Assisting with ... Account, please Sign-In before you apply.** **Job Description:** **Principle DFT Engineer ** Broadcom's ASIC Product Division is seeking candidates for a DFT… more
    Broadcom (03/14/25)
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  • HBM/DDR/SerDes DFT Verification Lead…

    Broadcom (San Jose, CA)
    …Broadcom's ASIC Product Division is seeking candidates for HBM/DDR/SERDES Verification Lead Engineer position at our San Jose, California Development Center. We ... seeking a highly skilled HBM and SerDes DFT Verification Engineer to join our dynamic team. In this role,... vectors before tape release. + Validating & Debugging Test vectors on ATE during the silicon… more
    Broadcom (02/19/25)
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  • Senior System Level Product Engineer

    NVIDIA (Santa Clara, CA)
    …a wide range of sectors. We are seeking post-silicon Senior System Level Product Engineer who is passionate and committed to making a difference in the world through ... this team, you are responsible for developing procedures and test specs for manufacturing line with an innate understanding...owners, Board Level teams, Product Engineering teams focused on ATE testing , operations to determine coverage needs and… more
    NVIDIA (02/01/25)
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  • Senior DFX Methodology Engineer

    NVIDIA (Santa Clara, CA)
    …the ATE with an understanding of pattern formats, failure processing, and test program development + Knowledge of DFT security and hardware system security ... We are now looking for a DFT Methodology Engineer ! NVIDIA has continuously reinvented itself over two...and intelligence. Make the choice to join us today. Design-for- Test Engineering at NVIDIA works on groundbreaking innovations involving… more
    NVIDIA (03/04/25)
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  • Senior DFT Engineer

    NVIDIA (Santa Clara, CA)
    …the ATE with an understanding of pattern formats, failure processing, and test program development + Strong programming and scripting skills in Perl, Python ... and intelligence. Make the choice to join us today. Design-for- Test Engineering at NVIDIA works on groundbreaking innovations involving...are growing fast. If you're a creative and autonomous engineer with real passion for technology, we want to… more
    NVIDIA (03/13/25)
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  • Senior Reliability Engineer

    Power Integrations (San Jose, CA)
    …life testing, reliability testing, statistical analysis, modeling of reliability data, ATE test data interpretation, device level electrical characterization, ... Senior Reliability Engineer Job Description: Perform reliability evaluation of IC...reliability engineering projects in support of product and process development projects. Assist in the design, selection and setup… more
    Power Integrations (01/22/25)
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  • DFT Engineer

    Broadcom (San Jose, CA)
    …complex and cutting edge network switching ASIC DFx (Design for Test /debug & manufacturability) from DFT architecture, to implementation, verification, timing ... closure, ATE pattern bringup. . You will also drive/push state...aggressively deliver low DPPM's, while optimizing the cost for test . Responsibilities + Drive the test quality… more
    Broadcom (03/11/25)
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  • Senior ASIC Design Engineer - Memory…

    NVIDIA (Santa Clara, CA)
    …emulation, prototyping, DFT, timing analysis, floor planning, ECO, bringup & lab debug, and ATE test development . + Strong working knowledge of Verilog or ... We are now looking for a Senior ASIC Design Engineer for Memory Controllers. As a Senior Designer at...BS or equivalent experience in Electrical Engineering or Computer Engineer or related degree required, advanced degrees (MS, PhD)… more
    NVIDIA (02/13/25)
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  • Senior Silicon Product Definition Engineer

    NVIDIA (Santa Clara, CA)
    …yield, and quality to define groundbreaking products as a product definition engineer for NVIDIA's family of chips and products. + Architect crucial next-generation ... teams. + Design tools to automate product definitions, binning, data collection, test case execution, and results analysis. + Build pre and post-silicon… more
    NVIDIA (03/04/25)
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  • Principal Silicon Circuits System Design…

    NVIDIA (Santa Clara, CA)
    …to hardware features, design requirements, silicon characterization needs, and test requirements. + Design essential next-generation product features that are ... multi-functional teams. + Design tools to automate product definitions, data collection, test case execution, and results analysis. + Find creative solutions to… more
    NVIDIA (03/06/25)
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