• Senior Timing Methodology Engineer

    NVIDIA (Santa Clara, CA)
    …work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the ... to optimize performance, yield, and reliability through increasingly comprehensive modeling , informative analysis, and automation. This work will influence the… more
    NVIDIA (01/17/25)
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  • Senior Signal and Power Integrity…

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior Signal & Power Integrity Engineer! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... creative Signal Integrity solutions to complex system design problems. + Modeling and Optimization of vias, connectors, sockets, breakouts and various system… more
    NVIDIA (03/12/25)
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  • Senior Manager, Data Science - PSM

    LinkedIn (Sunnyvale, CA)
    …York), India and Dublin. We leverage science and engineering to maximize the power of data. Our work spans member engagement, growth, marketing, sales, operations, ... by the business needs of the team. As the Senior Manager of Data Science for the PSM (Product...as define where to build scalable technology and aligned methodology across lines of business. * Build strong collaboration… more
    LinkedIn (03/15/25)
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  • Senior Signal Integrity Engineer (Hardware)

    Palo Alto Networks (Santa Clara, CA)
    …- just to name a few! At Palo Alto Networks, we believe in the power of collaboration and value in-person interactions. This is why our employees generally work full ... of Palo Alto Networks Firewall and SD-WAN hardware including: selecting components; modeling and simulating memory and serdes interfaces; modeling PDN networks;… more
    Palo Alto Networks (03/18/25)
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  • Senior ASIC Timing Engineer

    NVIDIA (Santa Clara, CA)
    …up with timing closure strategy, creating timing constraints, driving timing and power convergence, as well as ECO implementation + Apply knowledge and experience ... to improve timing convergence flows working with the methodology teams. What we need to see: + BS...of deep sub-micron process nodes and hands-on experience in modeling and converging timing in these nodes. Ways to… more
    NVIDIA (03/18/25)
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  • Senior ASIC Physical Design Engineer - High…

    NVIDIA (Santa Clara, CA)
    …closure of high-performance designs with a focus on improving PPA (Performance, Power , Area). + Good understanding of hardware architecture and RTL/logic design for ... Timing. + Knowledge of deep sub-micron process nodes and hands-on experience in modeling and converging high-performance designs in these nodes. Ways to stand out… more
    NVIDIA (01/08/25)
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  • Senior Director, HP Corporate Strategy

    HP Inc. (Palo Alto, CA)
    …* Project Management Professional (PMP) Certification **Knowledge & Skills** * Agile Methodology * Business Intelligence * Computer Science * Dashboard * Data ... Analysis * Data Management * Data Modeling * Data Quality * Data Science * Data...* Extract Transform Load (ETL) * Machine Learning * Power BI * Python (Programming Language) * R (Programming… more
    HP Inc. (01/12/25)
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