- Capgemini (San Francisco, CA)
- **Job Title: ASIC Design Verification Infrastructure Engineer (Modern Python experience is must)** **Job Location: Sunnyvale, CA (Remote work is OK)** ... US by Capgemini. **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _ASIC Design Verification Engineer (with modern Python programming)_… more
- Capgemini (San Francisco, CA)
- **Physical Design Engineer ** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip ... Timing with SI and OCV, Power, IR and Physical Verification at both block and chip level *Understanding constraints...**Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design … more
- Meta (Menlo Park, CA)
- …world-class complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure...hard IP identification, selection and integration 6. Collaboration with verification and emulation teams in test plan development and… more
- Capgemini (San Francisco, CA)
- **Job Title : Senior ASIC Physical Design Engineer ** **Job Location: Santa Clara, CA (Hybrid)** **Key Responsibilities** + Chip level floor planning, ... by Capgemini. **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior ASIC Physical Design Engineer_ **Location:** _CA-Santa Clara_ **Requisition… more
- Meta (Menlo Park, CA)
- …applications. The role also involves partnering with Full Stack Software, Hardware, ASIC Design , Verification , Emulation, Pre/Post-Silicon Validation & ... build and scale silicon for data center applications.As an ASIC Engineer in the Silicon Lifecycle Engineering...to guide future improvements. 3. Work directly with the design & verification team to enable a… more
- Meta (Menlo Park, CA)
- …world-class complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration. 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure...and hard IP identification, selection and integration. Collaboration with verification and emulation teams in test plan development and… more
- Meta (Menlo Park, CA)
- …world-class complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure...hard IP identification, selection and integration 5. Collaboration with verification and emulation teams in test plan development and… more
- Meta (Menlo Park, CA)
- …the architecture. 4. Work with a broad array of cross functional partners in ASIC design , verification , silicon bring-up, firmware and software development ... **Summary:** Meta Platforms Inc. is seeking an ASIC Engineer , Architecture to join our...in analyzing and driving power versus performance trade-offs in ASIC design . **Public Compensation:** $114,000/year to $166,000/year… more
- Capgemini (San Francisco, CA)
- …Area, but will consider remote.** **Job description:** . As an RTL Design Engineer you will be responsible for ASIC designs used in Memory Controllers, ... **RTL Design Engineer ** **Location: San Jose CA...applying linting and other (QC) quality checking and basic verification of designs. . Well versed in SystemVerilog Language… more
- Capgemini (San Francisco, CA)
- **Job Role:** **Physical Design (Synthesis) Engineer ** **Job Location : San Jose CA** **Job Description** + At least 7 years of experience in ASIC /SOC ... _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - Physical Design (Synthesis) Engineer_ **Location:** _CA-San… more
- Meta (Menlo Park, CA)
- …cycle of multiple generations of products 13. 2+ years of experience with designing ASIC verification & bring up hardware. 14. 3+ years of expertise with ... **Summary:** Meta is seeking a versatile Hardware Engineer to join our Compute Hardware team. Our...suppliers, to define product roadmap and program. 2. Specify, design , and develop CPU/GPU/ ASIC based compute hardware… more
- Meta (Menlo Park, CA)
- …cycle of multiple generations of products 13. 2+ years of experience with designing ASIC verification & bring-up hardware. 14. 3+ years of experience with ... **Summary:** Meta is seeking a versatile Hardware Engineer to join our Network Hardware team. Our...suppliers, to define product roadmap and program. 2. Specify, design , and develop ASIC based network hardware… more
- Capgemini (San Francisco, CA)
- …At least 5-8 years of experience in complex semiconductor services sales, particularly in ASIC design services. . Minimum of 5 years in Sales Pursuit Management. ... foundries, EDA companies, and IP providers. . Background in ASIC Design or Semiconductor Technology R&D is...towards Intelligent Industry. Capgemini Engineering has more than 55,000 engineer and scientist team members in over 30 countries… more