- Meta (Menlo Park, CA)
- …world-class complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge machine learning ASICs, capable of world class… more
- Meta (Menlo Park, CA)
- …world-class complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration. 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video… more
- Meta (Menlo Park, CA)
- …world-class complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video… more
- Capgemini (San Francisco, CA)
- **Physical Design Engineer ** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip ... **Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design ...**Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design Engineer_ **Location:** _CA-San Francisco_… more
- Capgemini (San Francisco, CA)
- **Job Title : Senior ASIC Physical Design Engineer ** **Job Location: Santa Clara, CA (Hybrid)** **Key Responsibilities** + Chip level floor planning, ... by Capgemini. **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior ASIC Physical Design Engineer_ **Location:** _CA-Santa Clara_ **Requisition… more
- Capgemini (San Francisco, CA)
- **Job Title: ASIC Design Verification Infrastructure Engineer (Modern Python experience is must)** **Job Location: Sunnyvale, CA (Remote work is OK)** **Job ... by Capgemini. **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _ASIC Design Verification Engineer (with modern Python programming)_ **Location:**… more
- Meta (Menlo Park, CA)
- …Co-work with internal silicon, architecture and system teams and externally engaged partners, ASIC design partners, foundry and OSAT and substrate vendors 6. ... **Summary:** Meta is looking for an experienced ASIC Packaging Engineer , Mechanical/Thermal modeling focus...ASIC R&D and manufacturing to drive the mechanical/thermal design using advanced FEA of new ASICs, and make… more
- Meta (Menlo Park, CA)
- …entire Silicon Lifecycle to build and scale silicon for data center applications.As an ASIC Engineer in the Silicon Lifecycle Engineering team, you will be part ... The role also involves partnering with Full Stack Software, Hardware, ASIC Design , Verification, Emulation, Pre/Post-Silicon Validation & Systems teams… more
- Meta (Menlo Park, CA)
- **Summary:** Meta Platforms Inc. is seeking an ASIC Engineer , Architecture to join our Infrastructure organization. This organization is responsible for building ... expert engineers to build "Green" data center accelerators. **Required Skills:** ASIC Engineer , Machine Learning Architecture (PhD) Responsibilities: 1.… more
- Meta (Menlo Park, CA)
- **Summary:** Meta is seeking a versatile Hardware Engineer to join our Accelerator Design team. Our mission is backed by a massive hardware infrastructure. Our ... our cutting-edge data centers, affecting billions of users. **Required Skills:** Hardware Engineer (Accelerator Design ) Responsibilities: 1. Specify, design ,… more
- Meta (Menlo Park, CA)
- **Summary:** Meta is looking for an experienced Silicon Packaging design Engineer for its Ecosystem and Technical Operation team to support the development of ... create as part of a world-class engineering team. **Required Skills:** Silicon Packaging Design Engineer Responsibilities: 1. Perform package design for… more
- Capgemini (San Francisco, CA)
- **RTL Design Engineer ** **Location: San Jose CA /...**Job description:** . As an RTL Design Engineer you will be responsible for ASIC designs ... . Develop micro architectural document from requirements specifications. . Extensive RTL design utilizing Verilog / SystemVerilog . Perform basic linting and other… more
- Capgemini (San Francisco, CA)
- **Job Role:** **Physical Design (Synthesis) Engineer ** **Job Location : San Jose CA** **Job Description** + At least 7 years of experience in ASIC /SOC ... _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - Physical Design (Synthesis) Engineer_ **Location:** _CA-San… more
- quadric.io, Inc (Burlingame, CA)
- …What We Expect: Initiative, Collaboration, Completion Role As a member of our physical design methodology team you will be tasked with developing physical design ... MS or Ph.D. in Electrical Engineering with a minimum of eight years of CPU/GPU/ ASIC implementation + Proficiency in TCL scripting + Proficiency in chip front-end and… more
- Meta (Menlo Park, CA)
- …and remote teams and suppliers, to define product roadmap and program. 2. Specify, design , and develop CPU/GPU/ ASIC based compute hardware solutions, and ASIC ... **Summary:** Meta is seeking a versatile Hardware Engineer to join our Compute Hardware team. Our...Support hyper-scale deployment and obtain learning for next generation design . 5. Collaborate with open source hardware community to… more
- Meta (Menlo Park, CA)
- …local and remote teams and suppliers, to define product roadmap and program. 2. Specify, design , and develop ASIC based network hardware solutions for use in our ... **Summary:** Meta is seeking a versatile Hardware Engineer to join our Network Hardware team. Our...front-end, scale-out and scale-up networks, and ASIC enabling hardware. 3. Lead the bring-up, validation, and… more
- Meta (Menlo Park, CA)
- …relevant technical field, or equivalent practical experience 6. 10+ years experience with analog design 7. Experience with ASIC design and tape-out cycles 8. ... Meta is seeking an experienced Analog Mixed Signal System Engineer to join our Platform HW team, focusing on...and bring-up of parallel links 2. Work closely with ASIC and SI teams to close links using Matlab… more
- Meta (Menlo Park, CA)
- …software and hardware technologies for AI at datacenter scale. Hardware Systems Engineer in RTP work closely with HW/SW co- design teams, hardware ... **Summary:** Meta is seeking a Hardware Systems Engineer to join our Release to Production (RTP)...work experience in one or more domains such as: ASIC development (Silicon design or bringup or… more
- Meta (Menlo Park, CA)
- …cutting-edge data centers affecting billions of users. Meta is seeking a passionate Electrical Engineer to join our Compute Hardware Design team. Our team is ... CPU, GPU, SoC, ASIC and/or FPGA, and related schematic and PCB design 9. Experience with analyzing and resolving power delivery related hardware issues 10.… more
- Meta (Fremont, CA)
- **Summary:** The Systems Integration Engineer (SIE) is responsible for the successful Integration of new hardware platforms & new infrastructure technologies into ... the data center. This includes leading the system design for serviceability (DFS) requirements development, implementation along with validating new data center… more