- Meta (Burlingame, CA)
- …the entire stack, from transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs, you will work ... test cases for multiple state of the art IPs. **Required Skills:** Design Verification Engineer Responsibilities: 1. Work with researchers and architects… more
- Capgemini (San Francisco, CA)
- **Job Title: Design Verification Infrastructure Engineer ** **Job Location: Sunnyvale, CA (Remote work is OK)** **Job Description:** **Key Responsibilities:** ... + .Assist the design verification leads to develop software for...towards Intelligent Industry. Capgemini Engineering has more than 55,000 engineer and scientist team members in over 30 countries… more
- quadric.io, Inc (Burlingame, CA)
- …progress on verification Requirements + At least 5 years of experience in design verification for CPU or GPUs. + Deep knowledge of leading verification ... Collaborate with architects, HW & SW designers to document verification test plans + Implement testbenches using commercial VIPs...drivers, assembly or C++ programs to efficiently test the design + Use coverage metrics to track and communicate… more
- Capgemini (San Francisco, CA)
- **Job role:** **Lead DV IP Verification Engineer ** **Job Location : San Francisco CA / Sunnyvale CA** **Job description:** Architect and Create verification ... **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - Lead DV IP Verification Engineer_ **Location:** _CA-San… more
- Siemens (San Francisco, CA)
- …are required + BSEE or equivalent, 10+ years of experience in semiconductor design , verification , and formal verification . EDA Functional Verification ... EDA Business is a global technology leader in electronic design automation software. Our software tools enable companies around.... **Position Overview:** The Product focused AE for Formal Verification will drive and grow Formal Verification … more
- Siemens (Fremont, CA)
- …full breadth of semiconductor and electrical systems solutions including integrated circuit design and verification , PCB design & manufacturing solutions, ... or a related discipline * A basic understanding of semiconductor logic design and verification * Basic skills in a hardware description languages (VHDL, SV, UVM,… more
- Capgemini (San Francisco, CA)
- **Physical Design Engineer ** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip ... Timing with SI and OCV, Power, IR and Physical Verification at both block and chip level *Understanding constraints...**Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design Engineer_ **Location:**… more
- Capgemini (San Francisco, CA)
- **RTL Design Engineer ** **Location: San Jose CA / Bay Area, but will consider remote.** **Job description:** . As an RTL Design Engineer you will be ... . Develop micro architectural document from requirements specifications. . Extensive RTL design utilizing Verilog / SystemVerilog . Perform basic linting and other… more
- Siemens (Fremont, CA)
- …EDA and MCAD tools that facilitate the architectural planning, physical design / verification , muti-die based electrical, thermal, mechanical stress analysis and ... drive the development of workflows to support the physical design planning, layout, and verification of advanced 3D IC designs. These workflows include package… more
- Capgemini (San Francisco, CA)
- **Job Title : Senior ASIC Physical Design Engineer ** **Job Location: Santa Clara, CA (Hybrid)** **Key Responsibilities** + Chip level floor planning, ... Timing with SI and OCV, Power, IR and Physical Verification at both block and chip level + Understanding...block and chip level + Understanding constraints and fixing design /timing techniques + Block level implementation from netlist to… more
- Abbott (Alameda, CA)
- …work for diversity, working mothers, female executives, and scientists. This Sr. Engineer role supports our next-generation biosensor product design and ... on** + Oversee and implement product algorithm test and verification from Systems perspective. + Design and...test and verification from Systems perspective. + Design and develop signal processing algorithm as needed to… more
- Abbott (Alameda, CA)
- …Our 114,000 colleagues serve people in more than 160 countries. This Sr. Engineer role supports our next-generation biosensor product design and development, ... focusing on clinical data analyses and sensor algorithm verification and improvement. **What you'll work on** + Support R&D product development data analysis need… more
- Meta (Menlo Park, CA)
- …SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to build...hard IP identification, selection and integration 6. Collaboration with verification and emulation teams in test plan development and… more
- Meta (Menlo Park, CA)
- …SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration. 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to build...and hard IP identification, selection and integration. Collaboration with verification and emulation teams in test plan development and… more
- Meta (Menlo Park, CA)
- …SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to build...hard IP identification, selection and integration 5. Collaboration with verification and emulation teams in test plan development and… more
- City and County of San Francisco (San Francisco, CA)
- …Deadline: Continuous How to Apply: Applications for Journey Information Systems Engineer - Networks Specialty are only accepted through an online process. ... that integrate these systems together as an enterprise networking backbone. The 1042 Networks Engineer is the journey level position in the Engineer series. The… more
- City and County of San Francisco (San Francisco, CA)
- …Deadline: Continuous How to Apply: Applications for Journey Information Systems Engineer - Applications Specialty are only accepted through an online process. ... integrate these systems together as an enterprise networking backbone. The 1042 Applications Engineer is the journey level position in the Engineer series. The… more
- AbbVie (Pleasanton, CA)
- …from research, product development and post market are effectively included in design verification related documentation, activities and outputs + Prepare ... according to regulated product development process + Hands-on experience with developing design verification protocols, execution, and report generation as well… more
- City and County of San Francisco (San Francisco, CA)
- …Application Deadline: Continuous How to Apply: Applications for Journey Information Systems Engineer - Systems Specialty are only accepted through an online process. ... these systems together as an enterprise networking backbone or platform. The 1042 Systems Engineer is the journey level position in the Engineer series. The… more
- City and County of San Francisco (San Francisco, CA)
- …Deadline: Continuous How to Apply: Applications for Journey Information Systems Engineer - Security Specialty are only accepted through an online process. ... that integrate these systems together as an enterprise networking backbone. The 1042 Security Engineer is the journey level position in the Engineer series. The… more