- Capgemini (San Francisco, CA)
- ** RTL Design Engineer ** **Location: San Jose CA / Bay Area, but will consider remote.** **Job description:** . As an RTL Design Engineer you will ... . Develop micro architectural document from requirements specifications. . Extensive RTL design utilizing Verilog / SystemVerilog . Perform basic… more
- Meta (Menlo Park, CA)
- …SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to build...development 3. RTL development using Verilog, System Verilog and HLS 4.… more
- Meta (Menlo Park, CA)
- …SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration. 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to build...development. 3. RTL development using Verilog, System Verilog and HLS. 4.… more
- Meta (Menlo Park, CA)
- …SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to build...development 3. RTL development using Verilog, System Verilog and HLS 4.… more
- Siemens (Fremont, CA)
- … methodology from RTL Synthesis to Physical Implementation phases o RTL Design /Verification, LEC, STA analysis o Integration and validation of ... Siemens EDA is a global technology leader in electronic design automation software. Our software tools enable companies around...the increasingly complex world of chip, board and system design . **Job Overview** Siemens EDA is seeking a senior… more
- Capgemini (San Francisco, CA)
- **Physical Design Engineer ** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip ... development, executing from the inception of the design ( RTL or gate netlist) through the...**Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design Engineer_ **Location:**… more
- Vector Atomic (Pleasanton, CA)
- …for EDA tools, preferably TCL or Python + Understanding of practical RTL design issues (latency, jitter, metastable behavior, hold/setup time, multicycle ... you! Position Summary We are seeking a Senior FPGA Engineer to join our team and contribute to the...requirements and select FPGA/SoC parts + Assist in the design of custom PCBs based on modern FPGA/SoC devices… more
- quadric.io, Inc (Burlingame, CA)
- …What We Expect: Initiative, Collaboration, Completion Role As a member of our physical design methodology team you will be tasked with developing physical design ... process nodes. Responsibilities + Develop Quadric processor IP implementation scripts from RTL to GDS across multiple advanced process nodes. + Preform test chip… more
- Vector Atomic (Pleasanton, CA)
- …role in shaping the future of quantum technology. Based on system goals, this engineer will design algorithms for instrument control. This task will combine ... you! Position Summary We are seeking a Senior DSP Engineer to join our team and play a pivotal...and optical engineers to create next-generation quantum instruments. + Design signal processing algorithms for precision sensors. The work… more
- quadric.io, Inc (Burlingame, CA)
- …floor of a revolutionary new processor architecture. As a senior member of our chip design team, you will contribute to all stages of the processor design cycle. ... processor architecture by understanding its applications + Own microarchitecture definition & RTL implementation of the processor in SystemC or SystemVerilog + Own… more
- quadric.io, Inc (Burlingame, CA)
- …Electrical Engineering or Computer Science + 7+ years of experience in FPGA design and implementation + Experience with FPGA and/or HAPS top-level systems Vivado or ... equivalent toolchain + Experience with implementing flows to map CPU/GPU RTL on FPGA based platforms for emulation purposes Responsibilities + Develop flows to run… more
- Capgemini (San Francisco, CA)
- …timing closure, top level test plans, and verification. . 15 years' experience with SoC design (Digital design and development RTL ) . Experience with chiplet ... Architecture but you will not be involved with the day-to-day details of the design . . Develop architecture and micro-architecture from specs (Full chip design … more
- Siemens (San Francisco, CA)
- **Req ID:** 415733 _Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to ... to deliver better products in the increasingly complex world of chip, board, and system design ._ **The Story** This is a unique opportunity to be part of a strategic… more