• ATE Test Engineer

    Google (Mountain View, CA)
    …Intellectual Property (IP) vendors to support structural validate and parametrically characterize the silicon . + Perform ATE test program development on ... Perl or other related language. + Experience with Automatic Test Equipment ( ATE ) test platforms...that power all of Google's services. As a Hardware Engineer , you design and build the systems that are… more
    Google (06/08/24)
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  • Staff Test Engineer

    Renesas (San Jose, CA)
    Staff Test Engineer Job Description Test ... coverage analysis, test H/W design, new silicon brings up ATE characterization, all the way ... device datasheet through characterization and DFT activities. As a test engineer , you are involved with the...debug skills on V93K platform + Hands-on experience on ATE test development for analog and high… more
    Renesas (06/27/24)
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  • Senior ASIC Engineer - Design-For-…

    NVIDIA (Santa Clara, CA)
    …fault simulation, and diagnosis + Experience with Silicon testing and Automatic Test Equipment ( ATE ) + Interest to grow technically and explore new fields ... We are now looking for a Senior ASIC Engineer - DFX Software. Do you like to...test pattern generation, application of these patterns on Silicon , failure analysis, and yield learning + Work with… more
    NVIDIA (05/29/24)
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  • Senior DFT Engineer , Hardware Compute…

    Amazon (Sunnyvale, CA)
    …failure analysis - Take high volume chips to production with high coverage ATE test program Basic Qualifications - BS degree in Computer Engineering/Electrical ... test and debug patterns for high coverage on silicon - Review sign-off level timing closure using static...closure. - Scripting (Perl/Tcl) - Experience in bringing up ATE test programs and taking complex SOC/ASIC… more
    Amazon (05/05/24)
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  • Senior Failure Analysis Engineer

    NVIDIA (Santa Clara, CA)
    …teams to verify and duplicate failures modes of failures that are reported on ATE , SLT, and appropriate test setups. + Drive continuous improvement initiatives ... physical failure analysis, advanced CMOS manufacturing/processes, circuit analysis, and automated test equipment ( ATE ). + Ability to understand and/or operate… more
    NVIDIA (06/06/24)
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  • Senior Product Engineer

    Power Integrations (San Jose, CA)
    Power Integrations, Inc. (http://www.power.com/) , is a Silicon Valley-based supplier of high-performance components used in high-voltage power conversion. Our ... standards worldwide. We are looking for a Sr. Product Engineer to drive the back-end development of these new...analysis and problem solving in a cross-functional team of Test , Process, Packaging, QA, Marketing and Applications Engineering. This… more
    Power Integrations (06/19/24)
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  • ASIC Engineering Technical Leader

    Cisco (San Jose, CA)
    …* Experience on pre- silicon DFT implementation and verification flows, and post- silicon test bring up procedures. * Verification skills include, System ... development of test benches to verify comprehensive Design-for- Test (DFT) architecture that supports ATE screening,...Work with the team on Innovative Hardware DFT & test strategy aspects for new silicon device… more
    Cisco (06/28/24)
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  • Senior DFT Engineer

    NVIDIA (Santa Clara, CA)
    …place-n-route and power, to ensure we are making the right trade-offs + Experience in Silicon debug and bring-up on the ATE with an understanding of pattern ... choice to join us today. We are now looking for a highly motivated DFT Engineer to join this dynamic and innovative hardware team at NVIDIA. Our Design-for- Test more
    NVIDIA (06/15/24)
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  • Senior DFX Methodology Engineer

    NVIDIA (Santa Clara, CA)
    …place-n-route and power, to ensure we are making the right trade-offs + Experience in Silicon debug and bring-up on the ATE with an understanding of pattern ... We are now looking for a DFT Methodology Engineer ! NVIDIA has continuously reinvented itself over two...and intelligence. Make the choice to join us today. Design-for- Test Engineering at NVIDIA works on groundbreaking innovations involving… more
    NVIDIA (04/06/24)
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  • Senior HSIO Engineer

    NVIDIA (Santa Clara, CA)
    …to our company and usher in the next wave of computing. NVIDIA's Silicon Solutions Group is responsible for crafting NVIDIA's GPUs and SoCs into groundbreaking ... + Coordinate with logic design, circuit design, board design, Simulation, diagnostics, ATE , firmware, driver, and marketing teams to drive the chip into production.… more
    NVIDIA (05/14/24)
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  • Senior DFT Engineer

    NVIDIA (Santa Clara, CA)
    …place-n-route and power, to ensure we are making the right trade-offs + Experience in Silicon debug and bring-up on the ATE with an understanding of pattern ... imagination and intelligence. Make the choice to join us today. Design-for- Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative… more
    NVIDIA (04/16/24)
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  • ASIC Engineering Technical Leader

    Cisco (San Jose, CA)
    …design signoff activities. What You'll Do * Responsible for implementing the Hardware Design-for- Test (DFT) features that support ATE , in-system test , debug ... Who You Are You are an ASIC Design for Test Hardware Engineer with 10+ years of...* Knowledge of the latest innovative trends in DFT, test and silicon engineering. * Experience with… more
    Cisco (06/28/24)
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  • 3D IC Solutions Engineer - DFT Design…

    Siemens Digital Industries Software (Fremont, CA)
    …tools: Siemens (Tessent), Synopsys (TestMAX), Cadence (Modus) + Experience in developing test strategies and solutions for integrated Silicon -on-Chip (SOC) IP ... final IC test hardware and working knowledge of commercial Automated Test Equipment ( ATE ) testers + Working knowledge of IC tools and design methods a plus:… more
    Siemens Digital Industries Software (05/30/24)
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  • 3D IC Solutions Engineer - Thermal/Stress…

    Siemens Digital Industries Software (Fremont, CA)
    …including: o RTL Design/Verification, Logic Syntheses, LEC, STA analysis o DFT integration and ATE test support a plus + Working knowledge of Advanced Packaging ... muti-die based electrical, thermal, mechanical stress analysis and manufacturing test of advanced 2.5 and 3D System-in-Package (SIP) designs. The… more
    Siemens Digital Industries Software (05/30/24)
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  • 3D IC Solutions Engineer - Package Design…

    Siemens Digital Industries Software (Fremont, CA)
    …Virtuoso) o Physical Verification: DRC, LVS, IR/EM analysis o DFT integration and ATE test support. + Working knowledge of Thermal/Stress analysis and/or optical ... muti-die based electrical, thermal, mechanical stress analysis and manufacturing test of advanced 2.5 and 3D System-in-Package (SIP) designs. The… more
    Siemens Digital Industries Software (05/26/24)
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  • 3D IC Solutions Engineer - Technical Lead

    Siemens Digital Industries Software (Fremont, CA)
    …Innovus, Virtuoso) o Physical Verification: DRC, LVS, IR/EM analysis o DFT integration and ATE test support. + Working knowledge of Advanced Packaging IC EDA ... muti-die based electrical, thermal, mechanical stress analysis and manufacturing test of advanced 2.5 and 3D System-in-Package (SIP) designs. The… more
    Siemens Digital Industries Software (05/26/24)
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  • Product Definer, Principal Member of Technical…

    Integense (San Jose, CA)
    …innovative, and passionate about providing smarter solutions to our customers. Our Automatic Test Equipment ( ATE ) group is rapidly expanding, and we're looking ... holistic system-level approach combined with creative circuit design, proprietary silicon process technology and materials engineering, to provide optimal...for a Sr. Product Definer / Systems Engineer to help chart the way. As a Technical… more
    Integense (06/26/24)
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  • Manager, Product Yield Engineering

    NVIDIA (Santa Clara, CA)
    …Influence Production yields to better improve the overall operation efficiency + Automate ATE Silicon Failure Analysis flows to help improve RMA detectability ... markets. What you'll be doing: + As Product Development Engineer Yield Manager, you will influence ASIC design to...to End yield monitoring systems + Build NVIDIA proprietary test algorithms codes using C++ and/or other computer language… more
    NVIDIA (06/07/24)
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