- SpaceX (Sunnyvale, CA)
- Sr. SOC /ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out ... ultimate goal of enabling human life on Mars. SR. SOC /ASIC PHYSICAL DESIGN ENGINEER (SILICON...issues, identify potential solutions and drive execution + Run, debug , and fix signoff closure issues in static timing… more
- SpaceX (Sunnyvale, CA)
- …hours and weekends as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer /Senior: $170,000.00 - $230,000.00/per year Your actual level and ... Sr. SOC /ASIC DFT Engineer (Silicon Engineering) Sunnyvale,...debug + Experience collaborating with cross-functional teams (eg, design , verification, and manufacturing) to ensure DFT features meet… more
- SpaceX (Sunnyvale, CA)
- ASIC/ SOC DFT Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars is ... the ultimate goal of enabling human life on Mars. ASIC/ SOC DFT ENGINEER (SILICON ENGINEERING) At SpaceX...and weekends as needed COMPENSATION AND BENEFITS: Pay range: Design Verification Engineer /Level I: $130,000.00 - $155,000.00/per… more
- NVIDIA (Santa Clara, CA)
- We are seeking a skilled Hardware Application Engineer to provide complete SoC product and platform support across the full hardware lifecycle. In this role, you ... design , or applications engineering. + Hands-on hardware bring-up, debug , and validation proficiency. + Experience supporting OEM/ODM customers...out from the crowd: + 3+ experiences on Notebook design , SoC , LPDDR5x + Experience with ARM,… more
- Google (Sunnyvale, CA)
- SoC DFT Engineer , Google Cloud _corporate_fare_...databases, software and hardware for logic and memory fail debug . + Design and Implement System Level ... and verification for SoCs. + Experience in silicon bring-up, debug , or validation of DFT features. + Experience with...industry-leading EDA tools for DFT, such as Synopsys (eg, Design Compiler, DFT Max) or Siemens EDA (eg, Tessent,… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Design for Debug (DFD) Architect and Methodology Engineer ! NVIDIA is seeking a DFD Architect to implement hardware and ... software solutions to debug world's leading SoC 's and GPU's. This...bus protocols, interconnect networks and/or caches. + Expertise in design for debug techniques and methodologies, integrated… more
- Meta (Sunnyvale, CA)
- …to build IP and System On Chip ( SoC ) for data center applications. As a Design Verification Engineer , you will be part of an agile team working with the best ... creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement IP/ SoC verification… more
- Meta (Sunnyvale, CA)
- …to build IP and System On Chip ( SoC ) for data center applications.As a Design Verification Engineer , you will be part of a agile team working with the ... creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement IP/ SoC verification… more
- Meta (Sunnyvale, CA)
- …creating a first-pass silicon success. 5. Furthermore, the ASIC Engineer , Design Verification will define and implement IP/ SoC verification plans, build ... Job" online on this web page. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Leverage ...debug , root-cause, and resolve functional failures in the design , partnering with the Design team. 8.… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer - DFX NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked ... the architecture, design , and verification of DFT IPs for cutting-edge SoC designs. + Develop, deploy, and enhance DFT methodologies for scalability and future… more
- Arrow Electronics (Mountain View, CA)
- …SoC test FW and create test plan documentation to cover ASIC features. * Develop and debug SoC ASIC platform test FW and specific tests in C/C++. * Partner in ... **Position:** Design Verification Engineer **Job Description:** Principal...Accountabilities * Responsible for architecting Verification Environment for ASIC SoC and providing verification support from defining verification plan… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …innovators who want to make an impact on the world of technology. We are looking for SoC /ASIC Digital Design Engineer with experience in Design for Test ... preferred. + Prior 5-15 years of professional experience in SoC /ASIC Digital Design with focus on ...Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals + Debug and… more
- Broadcom (San Jose, CA)
- …in some (or preferably all) of the following areas: + Experience with hardware design and debug , C++/SystemC and other programming languages are a strong plus. ... Description:** The ASIC Product Division in Broadcom, a leading supplier of state-of-the-art SoC and embedded IP, is looking for qualified individuals to work in … more
- Microsoft Corporation (Mountain View, CA)
- …engineers to help achieve that mission. We are looking for a **Senior Design Engineer ** to work in the dynamic Microsoft Artificial Intelligence System ... on Intellectual Property (IP) microarchitecture specification, Register Transfer Level (RTL) design , synthesis/Lint/CDC/FEV and System on Chip ( SOC ) integration… more
- Meta (Sunnyvale, CA)
- …from transistors, through architecture, firmware, and algorithms. **Required Skills:** Design Verification Engineer Responsibilities: 1. Define and implement ... and build test benches for block, IP, sub-system, and SoC level verification 2. Develop functional tests based on...Emulation and Silicon validation teams towards ensuring the highest design quality 5. Debug , root-cause and resolve… more
- Amazon (Cupertino, CA)
- …Qualifications - BS in Electrical Engineering or related technical field - 5+ years in RTL design for SOC - 5+ years of VLSI engineering - 5+ years with code ... of the Cloud-Scale Machine Learning Acceleration team you'll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia,… more
- Meta (Sunnyvale, CA)
- **Summary:** Electrical Design Validation Engineer in Wearables Hardware will be an integral member of the design verification + validation team that ensures ... visible and highly hands-on problem-solving environment. **Required Skills:** Electrical Design Validation Engineer Responsibilities: 1. Define electrical… more
- Applied Materials (Santa Clara, CA)
- …. **Position Overview** We are seeking an experienced FPGA Design Engineer with strong expertise in Xilinx Zynq SoC /MPSoC platforms and practical ... produce virtually every new chip and advanced display in the world. We design , build and service cutting-edge equipment that helps our customers manufacture display… more
- NVIDIA (Santa Clara, CA)
- …the choice to join us today. The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects of GPU and ... CPU clocking. The team collaborates with the front design team to understand the clocking requirements for the...we deliver clock RTL information to GPU, CPU and SOC verification team, timing and DFT teams. + Get… more
- NVIDIA (Santa Clara, CA)
- …looking for a Senior ASIC Design Engineer . NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC 's and GPU's. This position offers ... doing: + As a key member of the GPU Design team, you will implement, document and deliver high...and DMA engines. + Architect features to help silicon debug and support post-silicon validation activities. What we need… more