- Microsoft Corporation (Mountain View, CA)
- …of Artificial Intelligence and Computing. We are looking for a **Senior Silicon Engineer ** to join our team! If you are like tackling complex Register Transfer ... Logic ( RTL ) /Implementation challenges and have a keen interest in...checking tools, flows, and methods to our rapidly expanding RTL and physical design teams located across various sites… more
- Google (Sunnyvale, CA)
- …field, or equivalent practical experience. + 3 years of experience with RTL coding using Verilog/SystemVerilog. + 2 years of experience with industry-standard tools, ... role, you will join a team working on SoC-level RTL design for our data center accelerators. In this...transitions, and isolation strategies. + Take ownership of power signoff using industry standard tools coordinating deliverables from block… more
- Amazon (Sunnyvale, CA)
- …is powering the latest generation of Echo devices is looking for a Sr. SOC Design Engineer -STA to continue to innovate on behalf of our customers. We are a part of ... history. Roles & Responsibilities: - Includes definition and development of signoff methodology and corresponding implementation solution - Flow for STA, Crosstalk… more
- Cisco (San Jose, CA)
- …physical design Team which is responsible for full Chip physical implementation from RTL to GDSII. As Physical Verification Engineer your main responsibilities ... primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip...silicon validation phases with additional exposure to physical design signoff activities. What You'll Do You will be part… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out exploring ... goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets… more
- Cisco (San Jose, CA)
- …Jose, CA with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT ... and post silicon validation phases with additional exposure to physical design signoff activities. What You'll Do * Responsible for implementing the Hardware… more
- Cisco (San Jose, CA)
- …Jose, CA with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT ... flow and post silicon validation phases with additional exposure to physical design signoff activities. What You'll Do * Responsible for thorough test planning and… more
- Amazon (Cupertino, CA)
- …of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and architectures, while ensuring ... to improve turnaround times for physical design work. Interface directly with RTL , Physical Design, Package Design, DFT and other teams to improve methodologies… more
- Broadcom (San Jose, CA)
- …looking for highly skilled engineers that want to be part of an RTL to GDS team, enabling high-speed chip implementations, reducing power, increasing performance and ... - Expertise in Physical Design, Synthesis, EM/IR, Physical Verification, Timing Signoff - Understanding of Clock structures, Power optimization, DFT - Deep… more