- NVIDIA (Santa Clara, CA)
- …integral part of the SOC Design team to develop and improve our RTL top - level assembly process and tool set + Top - level assembly: Test new ... The NVIDIA SOCD CAD team is looking for a top engineer with proven experience in hardware design...roadmap to address upcoming project challenges for top - level assembly + Create complex GPU, SOC ,… more
- NVIDIA (Santa Clara, CA)
- …) group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design ... We are looking for SOC Design Engineer! The complexity of...complex GPU and Tegra chips and interface, directly with unit- level ASIC, Physical Design , CAD, Package … more
- NVIDIA (Santa Clara, CA)
- …) group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design ... Are you looking for an SOC Design Engineer opportunity? If yes,...sophisticated GPU and Tegra chips and interact directly with unit- level ASIC, Physical Design , CAD, Package … more
- Google (Sunnyvale, CA)
- …performance, efficiency, and integration. In this role, you will join a team working on SoC - level RTL design for our data center accelerators. You'll own ... instantiation, customization and generation of RTL. + Experience with SOC implementation standards and interfaces (eg AXI). + Experience...top - level RTL, architecture, design , and implementation of… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …using our components. The CSG Central Applications Engineering team seeks an experienced and talented SoC Design Manager to lead a new team for CSG systems. In ... Our IP designs are used by most of the top semiconductor vendors today, and our customers are shipping...will be responsible for managing a team of hardware design engineers to develop and validate reference systems for… more
- Meta (Sunnyvale, CA)
- …the ML accelerator. 2. Define and track detailed internal integration test plans for top - level design components, and SOC vendor test plans and use case ... and/or C/C++ based verification. 11. 10+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies. 12.… more
- Meta (Sunnyvale, CA)
- …3+ years of experience as a Digital Design Engineer. 9. Experience with top level integration using automation tools. 10. Experience in RTL coding, synthesis ... Digital Design Engineer Responsibilities: 1. Responsible for top - level or block level uArchitecture...and/or SoC Integration. 11. Experience in digital design … more
- NVIDIA (Santa Clara, CA)
- …C/C++ is essential. + Be familiar with hierarchical design approach, top -down design , SoC and system level verification. NVIDIA is on the move and ... Accelerated UVM Testbenches). + Bring up SOCs on emulation, root causing SoC /Processor test fails and emulator environment issues. + We have continual collaboration… more
- Amazon (Cupertino, CA)
- …the right trade-offs. Key job responsibilities - integrate multiple subsystems into top level SOC , ensure correct clock/reset/functional/DFT signal routing ... Engineering or related technical field - 5+ years of experience in RTL design for SOC - 5+ years of experience VLSI engineering - 5+ years of experience… more
- Cisco (San Jose, CA)
- …issues, provide solutions and ensure signoff clean results * Work with block and top level implementation teams to understand physical aspects and feedback on ... necessary updates * Work closely with block and TOP level physical implementation, IP development teams...with semiconductor foundries on installation, and maintenance of process design kits (PDKs) for SOC physical … more
- NVIDIA (Santa Clara, CA)
- …HSpice, Finesim, XA) + Experience in crafting test bench environments for component and top level circuit verification + Expertise in System Verilog or similar ... We are looking for an Engineer to verify the design and implementation of the world's leading SoC 's and GPU's. This position offers the opportunity to have real… more
- Meta (Sunnyvale, CA)
- …verification and UVM methodology. 10. 5+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies. 11. ... and track detailed test plans for the different modules and top levels. 3. Drive Design Verification to closure based on defined verification metrics on test… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …emulation platform used for emulating complex custom silicon designs used by top semiconductor industries globally . The Palladium platform is a scalable emulation ... power devices into complex scalable enterprise grade hardware. The design / verification / physical design of...or Master's + Experience in RTL development of complex ASIC/ SoC . + Comfortable in Verilog and SystemVerilog for the… more
- Cisco (San Jose, CA)
- …Verilog and UVM methodology * Prior experience in verifying complex blocks, clusters and top level for SoC * Prior experience building testbenches from ... for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers...that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through… more
- Insight Global (Sunnyvale, CA)
- …customer Physical Design Implementation team members Experience with top - level floorplanning, bump-maps, RDL IO Pad/Ring creation/verification, power grid ... SOC development objectives. You will be doing Physical design for SOC verification and chip engineering... clocking methodologies (H-Tree, Structure Clocking, MS CTS for Top /Blocks with push/down & bottoms up approaches) Highly proficient… more
- NVIDIA (Santa Clara, CA)
- …of the Data-Center-on-a-Chip Architecture (DOCA). You will be among the very first to design systems for NVIDIA's next-generation SoC and take part in defining ... data science, and AI. What you'll be doing: + Architect, design , and develop innovative, scalable, performant hardware-accelerated software products to run… more
- Meta (Sunnyvale, CA)
- …8. Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top - level including SOC . Analyze the inter-block timing and come up ... CDC analysis, timing constraints, synthesis to build efficient System on Chip ( SoC ) and IP for data center applications. **Required Skills:** ASIC Engineer,… more
- Microsoft Corporation (Mountain View, CA)
- …and development. + Build solid engineering plans, with bottoms up schedule, drive trade off, design decisions to meet top level schedule on time and with ... programing skills, with experience with SoC Architecture and Design , writing low level drivers, root causing issues at the intersection of multiple… more
- Cisco (San Jose, CA)
- …ASIC verification using UVM/System Verilog. * Prior experience verifying complex blocks, clusters and top level for SoC * Prior experience building test ... success in high-performance/high-volume semiconductor markets. * Architect block, cluster and top level DV environment infrastructure * Create DV infrastructure… more
- Actalent (Mountain View, CA)
- …Day in the Role Purpose of the Team: The purpose of this team is : FPGA Design Verification, System level debug, Filing bugs The role will consist of: + Very few ... beginning and a lot of simulations work + Understanding design spec, creating testbench, running simulation, finding bugs. +...role would turn to support the platform and system level testing that we are developing while still working… more