• Senior ASIC Design Engineer - Memory

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior ASIC Design Engineer for Memory Controllers. As a Senior Designer at NVIDIA, you'll join a group of hardworking engineers to ... design and implement innovative Memory Controllers for our GeForce GPUs and Tegra SoCs....the micro-architecture and design including RTL design, synthesis, functional verification and timing analysis using groundbreaking CAD tools and… more
    NVIDIA (08/14/24)
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  • Senior Applications Engineer - DDR Design…

    Cadence Design Systems, Inc. (San Jose, CA)
    …devices.Responsibilities include:* Technical presales of Memory IP* Gain expertise in memory controller and PHY IPs and DDR protocols* Work closely with ... - DDR4/5, LPDDR4/5/5X, HBM2/3, GDDR6* Perl/Python Scripts* Experience on memory subsystem verification and/or performance analysis* Strong...design* Knowledge of AXI, DFI protocols* Working knowledge of memory controller and memory PHY… more
    Cadence Design Systems, Inc. (09/17/24)
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  • Sr. DDR IP Design Engineer (Silicon Engineering)

    SpaceX (Sunnyvale, CA)
    …the Starlink network. RESPONSIBILITIES: + Own the high quality release of the Memory Controller IP for SpaceX SoC designs, including triaging release/integration ... issues into IP defects and addressing issues + Responsible for Memory Controller /PHY IP core development and integration + Responsible for RTL design, synthesis,… more
    SpaceX (07/22/24)
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