- Capgemini (Santa Clara, CA)
- …US by Capgemini. **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _Sr. Logic Design ( RTL ) Engineer_ **Location:** _CA-Santa Clara_ ... **Location: San Clara, California.** **Job description:** The RTL Engineer performs detailed block design ...description:** The RTL Engineer performs detailed block design from system requirements and evolving specifications. Perform … more
- Google (Mountain View, CA)
- …a related field, or equivalent practical experience. + 5 years of experience with digital logic design principles, RTL design concepts, and languages ... such as Verilog or SystemVerilog. + Experience with logic synthesis techniques to optimize RTL code,...Contribute to CPU frontend designs, emphasizing on microarchitecture and RTL design for the next generation CPU.… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …includes but is not limited to: + Digital microarchitecture definition and documentation + RTL logic design , debug and functional verification + IP ... and developing flows at all phases of the digital design and functional verification. It is further expected that...Substantial experience with Verilog is required, as are excellent logic and debug skills. Engineering expertise in mixed-signal IP… more
- Google (Mountain View, CA)
- …a related field, or equivalent practical experience. + 5 years of experience with digital logic design principles, RTL design concepts, and languages ... with an emphasis on computer architecture. + 10 years of experience with digital logic design principles, RTL design concepts, and languages such as… more
- NVIDIA (Santa Clara, CA)
- …with industry-standard tools. Deep understanding of hardware architecture and hands-on skills in RTL / logic design for timing closure. + Experience in ... We are now looking for a motivated ASIC Physical Design Engineer, Netlisting to join our dynamic and growing...equivalent experience) with 2 years' experience. + Expertise in logic equivalence checking/FV required from RTL to… more
- NVIDIA (Santa Clara, CA)
- …improving PPA (Performance, Power, Area). + Good understanding of hardware architecture and RTL / logic design for timing closure, specifically experience in ... + Work in a cross-functional environment interacting with multiple teams, including Architecture and RTL team, to solve complex design problems as well as build… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Logic Design Engineer! Asa member of our CPU Logic Design Team, you will be responsible for the design of CPU ... is a deep understanding of ASIC design flow including RTL design , verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO,… more
- NVIDIA (Santa Clara, CA)
- …required as is a deep understanding of ASIC design flow including RTL design , verification, logic synthesis, prototyping, DFT, timing analysis, ... We are now looking for a Logic Design Engineer with Physical ...closure as well as working on micro-architectural definition and RTL coding/debug. This position offers you the opportunity to… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer to join...Boot controllers. + You will be responsible for the RTL design , logic synthesis, and ... design concepts and experience in ASIC design flow including RTL design , verification, logic synthesis and timing analysis + Strong coding skills in… more
- NVIDIA (Santa Clara, CA)
- We are now hiring for a Senior Logic and Digital Circuit Design Engineer! NVIDIA has continuously reinvented itself over two decades. Our invention of the ... deep understanding of Verilog or SystemVerilog, logic design and circuit modeling in RTL for...logic design and circuit modeling in RTL for mixed-signal blocks; Experience with industry standard verification… more
- Broadcom (San Jose, CA)
- …not required 1. Exposure to SERDES communications protocols. 2. Logic design , chip architecture, microarchitecture, Verilog RTL coding 3. Front-end logic ... globe connected. Our ASIC products division is looking for senior , physical design engineering veterans to guide...design verification and sign-off. 6. Knowledge of ASIC design flow including physical design , logic… more
- SpaceX (Sunnyvale, CA)
- …for Memory Controller/PHY IP core development and integration + Responsible for RTL design , synthesis, timing constraints, power estimation, and timing analysis ... Sr . DDR IP Design Engineer (Silicon Engineering)...years of experience working with ASICs and the VLSI design flow + Experience in RTL development and… more
- NVIDIA (Santa Clara, CA)
- …networks and/or caches. + Great understanding of ASIC design flow including RTL design , verification, logic synthesis and timing analysis. + Exposure ... We are now looking for a Senior ASIC Design Engineer. NVIDIA is...document and deliver high performance, area and power efficient RTL to achieve design targets and specifications.… more
- NVIDIA (Santa Clara, CA)
- …years in a leadership role + Expertise in Verilog or SystemVerilog, logic design , and circuit modeling in RTL for mixed-signal blocks + Strong background in ... Are you looking for a Digital Design Manager role? As a Senior Digital Design Manager in our Mixed-Signal High-Speed I/O SerDes group, you'll lead a team… more
- SpaceX (Sunnyvale, CA)
- Sr . SOC/ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out ... the ultimate goal of enabling human life on Mars. SR . SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)...drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL / design … more
- Qualcomm (Santa Clara, CA)
- …route, timing and power use, and verification or similarly for custom circuit design /layout flow. * Utilizes tools/applications (eg, RTL to GDS Flow, Virtuoso) ... team you will be working on WiFi (802.11x) technology, SOC Design , Low Power micro-architecture, Power Intent/Implementation, power estimates and power reduction… more
- NVIDIA (Santa Clara, CA)
- …silicon visibility tools. + Great understanding of ASIC design flow including RTL design , verification, logic synthesis, timing analysis and bringup. + ... We are now looking for a Senior Design for Debug (DFD) Architect...bus protocols, interconnect networks and/or caches. + Expertise in design for debug techniques and methodologies, integrated logic… more
- NVIDIA (Santa Clara, CA)
- … design . + A deep understanding of ASIC design flow including RTL design , verification, logic synthesis, timing analysis, ECO, and post silicon ... NVIDIA is seeking an outstanding Senior ASIC Design Engineer to ...relevant work or research experience. + Highly proficient in logic design , Verilog and/or System-Verilog, with a… more
- Microsoft Corporation (Mountain View, CA)
- …Computer Science, or related field. + 3+ years experience in digital logic design in SystemVerilog/Verilog/VHDL + 3+ years experience running synthesis/static ... clients, and augmented reality. We are looking for a ** Senior ** **Silicon** ** Design Engineer** to work on...responsible for leading the microarchitecture and Register Transfer Level ( RTL ) implementation of custom IP blocks, working with a… more
- NVIDIA (Santa Clara, CA)
- …experience. + Ability to thrive in a dynamically changing environment. + Experience in RTL design (Verilog), verification and logic synthesis. + Strong ... and CPU clocking. The team collaborates with the front design team to understand the clocking requirements for the...with other architects, ASIC designers and verification engineers to design high frequency clocks. + You should be able… more