• CPU DFT Engineer

    Qualcomm (Santa Clara, CA)
    …digital transformation to help create a smarter, connected future for all. As a DFT Engineer you will work with chip architects, chip designers, implementation ... + 5+ years of practical experience with test or DFT + Experience using the Mentor Tessent ...with a disability and need an accommodation during the application /hiring process, rest assured that Qualcomm is committed to… more
    Qualcomm (11/01/24)
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  • ASIC Design for Test Engineer

    Cisco (San Jose, CA)
    The application window is expected to close on 11/23/2024 This is an onsite role and will require working out of the Milpitas/San Jose office location. Who We Are ... physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a...experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime * Prior experience working with… more
    Cisco (11/01/24)
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