- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for ... designs, with focus on CAD and automation. + Develop custom flows for validating QoR of ETM models, both...+ Collaborate with technology leads, VLSI physical design, and timing engineers to define and deploy the most sophisticated… more
- Google (Sunnyvale, CA)
- …final timing sign-off for complex ASICs. + Participate in both static timing analysis methodology development and support, as well as chip implementation and ... 5 years of experience in the domain of static timing analysis. (ie, constraint authoring and verification, static ...or more aspects of physical design or physical design flow/ methodology , to successful tape-outs and shipping silicon. + Experience… more
- Meta (Sunnyvale, CA)
- …serdes. 17. Familiarity to next generation memory and chiplet standards and timing budget methodology . 18. Package-level signal integrity and power integrity ... **Summary:** Meta is looking for an experienced ASIC Packaging Engineer , Signal Integrity, and Power Integrity focus for its...its ASIC packaging team to support the development of custom Silicon for Infrastructure as well as to develop… more
- Meta (Sunnyvale, CA)
- …(SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical design implementation ... logic synthesis, floorplan, place and route, clock tree synthesis, static timing analysis, IR drop, EM, and physical verification in advanced technology… more
- Qualcomm (Santa Clara, CA)
- …envelope on performance, energy efficiency and scalability. As CPU Physical Design CAD engineer , you will build and support the world's best implementation tools and ... flows. Your tools and flows will ensure our custom CPUs have industry-leading power, performance and area. Roles...our high-performance place-and-route CAD flow + Architect and recommend methodology improvements to ensure our silicon has the best… more
- Google (Sunnyvale, CA)
- …speed serdes. + Familiarity to next generation memory and chiplet standards and timing budget methodology . + Excellent programming and data analysis skill with ... with cross-functional teams, including chip top design, physical design, Static Timing Analysis (STA), package, and system teams. + Experience with 2.5D/3D… more
- Google (Sunnyvale, CA)
- …bus protocols. Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll ... and control subsystem, also participate in developing infrastructure and methodology that form the foundation of our SoCs (ie,...design teams to ensure design meets physical requirements and timing closure. Google is proud to be an equal… more