- Broadcom (San Jose, CA)
- …PhD in Electrical Engineering or Computer Engineering with 10+ years of experience in Physical design . + Deep knowledge about industry standards in Physical ... Power-grid and high speed clock constraints and specification. + Good understanding of physical design verification methodology to debug LVS/DRC issues at the… more
- Capgemini (San Francisco, CA)
- …memory interface considering Input/Output Physical Layer (IO PHY), SI/PI and physical design . **Required Skills:** *Bachelor or Master degree in Electrical ... impedance in lab to correlate simulation results and improve design flow *Work closely with Architecture, ASIC ,... and software to support the convergence of the physical and digital worlds. Coupled with the… more
- Cisco (San Jose, CA)
- … ASIC team can provide. You will work with exceptional talent with vast ASIC design and development expertise. With Cisco being a systems company, you will ... refining design and timing constraints for seamless physical design closure. As part of this...Experience with microarchitecture and RTL implementation. * Experience with digital design concepts (eg. clocking and async… more
- Cisco (San Jose, CA)
- …You will work with outstanding talent and vast ASIC development expertise in design , DV, DFT, physical design , and post-silicon validation The team ... What You'll Do * You will participate in the ASIC design verification for Cisco high-end switching...develop innovative technology, and to power a more inclusive, digital future for everyone. How do we do it?… more
- Cisco (San Jose, CA)
- …programming experience. * Experience with digital concepts and fundamentals of ASIC design principles. * Interactive and waveform debug experience. Preferred ... achieve coverage closure. * Collaborate with the verification and physical design teams to resolve block level...in Electrical or Computer engineering and 5+ years of ASIC Design experience or Master's degree in… more
- Capgemini (San Francisco, CA)
- …generation memory interface considering Input/Output Physical Layer (IO PHY), SI/PI and physical design . **Required Skills** + 8 years of experience in SIPI ... impedance in lab to correlate simulation results and improve design flow. + Work closely with Architecture, ASIC... and software to support the convergence of the physical and digital worlds. Coupled with the… more
- Cisco (San Jose, CA)
- …basis to address design bugs and close code coverage. * Work closely with physical design team to close design timing and place-and-route issues * ... Do Be part of the development organization as an ASIC Engineering Technical Leader with primary focus on RTL... Engineering Technical Leader with primary focus on RTL Design . * Create micro-architecture specifications and participate in reviews… more
- Cisco (San Jose, CA)
- …focus on Design -for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements ... be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with...participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device… more
- Cisco (San Jose, CA)
- …lead in San Jose, CA. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive high-quality DFT ... hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various… more
- Google (Mountain View, CA)
- … design . + Knowledge of ASIC Verification, DFT, synthesis, STA, or Physical Design . + Knowledge of high performance and low-power design techniques. ... with an emphasis on computer architecture. + Experience with ASIC design methodologies for clock domain checks,...enhancements + Work with the multi-site cross-functional teams: Verification, Design for Test, Physical Design … more
- Broadcom (San Jose, CA)
- … design trade-offs. You will collaborate closely with verification engineers and physical design teams to ensure functional correctness, timing closure, and ... and Timing Closure:** + Perform synthesis and work with physical design teams to achieve timing closure...or similar. + **Knowledge Areas:** + Solid understanding of digital design fundamentals such as pipelining, FSMs,… more
- quadric.io, Inc (Burlingame, CA)
- …Happiness What We Expect: Initiative, Collaboration, Completion Role As a member of our physical design methodology team you will be tasked with developing ... physical design methodologies and automation scripts for...technologies. Nice to haves: + Knowledge of lower power digital design techniques. + IP integration experience.… more
- Capgemini (San Mateo, CA)
- …including strategic account development in complex semiconductor services sales, particularly in ASIC design services and sales pursuit management with at least ... foundries, EDA companies, and IP providers. + Background in ASIC Design or Semiconductor Technology R&D is... and software to support the convergence of the physical and digital worlds. Coupled with the… more
- Capgemini (San Francisco, CA)
- …At least 5-8 years of experience in complex semiconductor services sales, particularly in ASIC design services. + Minimum of 5 years in Sales Pursuit Management. ... foundries, EDA companies, and IP providers. + Background in ASIC Design or Semiconductor Technology R&D is... and software to support the convergence of the physical and digital worlds. Coupled with the… more
- Broadcom (San Jose, CA)
- …accurate and efficient timing analysis and closure. Expertise in place-and-route tools for ASIC /SoC design is a must. The ideal candidate should have strong ... Sign-In before you apply.** **Job Description:** Broadcom is looking for a ** Design Implementation Engineer** with demonstrated expertise across key areas such as… more
- Western Digital (San Jose, CA)
- …to make what you thought was once impossible, possible. At our core, Western Digital is a company of problem solvers. People achieve extraordinary things given the ... platforms for business, creative professionals, and consumers alike under our Western Digital (R), WD(R), WD_BLACK (TM) , and SanDisk(R) Professional brands. We are a… more
- Capgemini (San Francisco, CA)
- …cutting-edge technologies in digital and software to support the convergence of the physical and digital worlds. Coupled with the capabilities of the rest of ... **Job Location:** **San Francisco CA** **Job Description** We are seeking Senior Design Verification Engineer for our Full Time role with Capgemini Engineering.… more
- Broadcom (San Jose, CA)
- …high performance System-On-Chip ASICs. Key competencies required are: + Working experience in ( digital ) physical design implementation of large scale ASICs ... Demonstrated strong technical hands-on competency in using leading edge physical design EDA tools in projects. +...challenges of designing in deep sub-micron processes and state-of-the-art ASIC design for AI/ computing and networking… more
- Broadcom (San Jose, CA)
- …industry for IP and chip design + Working knowledge of IP and chip design flow for analog and digital + Experience with parametric and yield data analysis. ... extraction and simulation, abstract and LEF/DEF generation, LVS/ERC checks, physical verification + Conducting design reviews &...from manufacturing, technology and packaging **Job Description** + Provide design support for IP & ASIC to… more
- Broadcom (San Jose, CA)
- …debug and yield improvement to meet the product test metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role could ... analysis, diagnostics & yield improvement efforts + Interfacing with the customer, physical design and test engineering/manufacturing teams located globally +… more