• ASIC Engineer , Design

    Meta (Menlo Park, CA)
    …world-class complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge machine learning ASICs, capable of world class… more
    Meta (12/11/24)
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  • ASIC Engineer , Design

    Meta (Menlo Park, CA)
    …world-class complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration. 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video… more
    Meta (10/09/24)
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  • ASIC Engineer , Design

    Meta (Menlo Park, CA)
    …world-class complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video… more
    Meta (10/16/24)
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  • Senior E/E & Semiconductor Engineer

    Capgemini (San Francisco, CA)
    **Physical Design Engineer ** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip ... **Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design ...**Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design Engineer_ **Location:** _CA-San Francisco_… more
    Capgemini (10/16/24)
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  • Senior ASIC Physical Design

    Capgemini (San Francisco, CA)
    **Job Title : Senior ASIC Physical Design Engineer ** **Job Location: Santa Clara, CA (Hybrid)** **Key Responsibilities** + Chip level floor planning, ... by Capgemini. **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior ASIC Physical Design Engineer_ **Location:** _CA-Santa Clara_ **Requisition… more
    Capgemini (10/16/24)
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  • ASIC Design Verification…

    Cisco (San Jose, CA)
    …You'll Work With: You will be in the Silicon One development organization as an ASIC design verification engineer in San Jose, CA. You collaborate closely ... hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various… more
    Cisco (11/01/24)
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  • ASIC Design Verification…

    Capgemini (San Francisco, CA)
    **Job Title: ASIC Design Verification Infrastructure Engineer (Modern Python experience is must)** **Job Location: Sunnyvale, CA (Remote work is OK)** **Job ... by Capgemini. **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _ASIC Design Verification Engineer (with modern Python programming)_ **Location:**… more
    Capgemini (01/03/25)
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  • ASIC Digital Design Engineer

    Qualcomm (San Jose, CA)
    …a smarter, connected future for all. As a Qualcomm Digital ASIC Engineer , you will define, model, design , optimize, verify, validate, implement, and document ... in Science, Engineering, or related field and 4+ years of ASIC design , verification, validation, integration, or related work experience. OR Master's degree… more
    Qualcomm (12/23/24)
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  • ASIC Design Engineer

    Cisco (San Jose, CA)
    …the lab. Who You'll Work With You will work with exceptional talent with vast ASIC design and development expertise. With Cisco being a systems company, you will ... degree in Electrical or Computer engineering. * 8+ years of ASIC Design experience. * Excellent Verilog/System Verilog programming skills. * Possesses… more
    Cisco (11/15/24)
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  • ASIC Design Engineer

    Cisco (San Jose, CA)
    …the lab. Who You'll Work With You will work with exceptional talent with vast ASIC design and development expertise. With Cisco being a systems company, you will ... degree in Electrical or Computer engineering. * 4+ years of ASIC Design experience. * Excellent Verilog/System Verilog programming skills. * Possesses… more
    Cisco (11/08/24)
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  • ASIC Design Engineer

    Cisco (San Jose, CA)
    …in Electrical Engineering, Computer Science or related degree with 5+ years of ASIC design experience or Masters degree in Electrical Engineering, Computer ... Science or related degree with 3+ years of ASIC design experience * Experience in Verilog/System Verilog programming skills. * Experience in interactive and… more
    Cisco (11/27/24)
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  • ASIC Rtl Design Engineer

    Broadcom (San Jose, CA)
    …Verilog + Strong experience in Tcl, Perl, Python scripting + Good understanding of ASIC design flow + Strong interpersonal skills and an excellent team player ... for an experienced RTL Designer for our team. The engineer will be responsible for design & development of digital circuits including defining the architecture.… more
    Broadcom (11/01/24)
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  • ASIC Design Engineer

    Google (Mountain View, CA)
    …field, or equivalent practical experience. + 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or ... techniques to improve RTL code, performance and power as well as low-power design techniques. + Experience with ARM-based SoCs, interconnects and ASIC more
    Google (12/10/24)
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  • ASIC Design Verification…

    Cisco (San Jose, CA)
    …Bachelor's Degree in EE, CE, or other related field. * 7+ years of related ASIC design verification experience. * Proficient in ASIC verification using ... design in emulation. * Oversee and manage the ASIC bring-up process. Who You Are The Core Hardware...is on the lookout for a driven Senior Verification Engineer to join us in developing the next generation… more
    Cisco (12/31/24)
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  • ASIC Design Verification…

    Cisco (San Jose, CA)
    …to first customer shipments. What You'll Do * You will participate in the ASIC design verification for Cisco high-end switching products. * Development of ... years of related experience * Experience in System Verilog/UVM. * Experience with ASIC design and verification processes, debugging, methodology, and tools. *… more
    Cisco (10/28/24)
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  • Digital ASIC Micro Architect Design

    Google (Mountain View, CA)
    …computer architecture concepts, including microarchitecture, multimedia architecture, and silicon design . Preferred qualifications: + Master's degree or Phd in ... codecs, display, computer cores and machine learning accelerators). + Experience in ASIC development methodology and require Verilog RTL development as per the… more
    Google (12/10/24)
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  • ASIC Digital Physical Design

    Broadcom (San Jose, CA)
    …Electrical Engineering or Computer Engineering with 10+ years of experience in Physical design . + Deep knowledge about industry standards in Physical Design , ... and high speed clock constraints and specification. + Good understanding of physical design verification methodology to debug LVS/DRC issues at the chip and block… more
    Broadcom (11/01/24)
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  • ASIC Design Verification…

    Broadcom (San Jose, CA)
    …efficiency._** **_We are looking for highly skilled and efficient Constrained Random Design Verification engineers that want to verify new designs that can evolve ... of devices. The candidate will work with our worldwide design and architecture teams to develop leading edge products....teams to develop leading edge products. All aspects of Design Verification will be involved, along with opportunities for… more
    Broadcom (11/06/24)
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  • ASIC Design for Test Engineer

    Cisco (San Jose, CA)
    …hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various ... be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with...in San Jose, CA with a primary focus on Design -for-Test. You will work with Front-end RTL teams, backend… more
    Cisco (11/01/24)
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  • ASIC Packaging Engineer

    Meta (Menlo Park, CA)
    …Co-work with internal silicon, architecture and system teams and externally engaged partners, ASIC design partners, foundry and OSAT and substrate vendors 6. ... **Summary:** Meta is looking for an experienced ASIC Packaging Engineer , Mechanical/Thermal modeling focus...ASIC R&D and manufacturing to drive the mechanical/thermal design using advanced FEA of new ASICs, and make… more
    Meta (11/14/24)
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