- Cadence Design Systems, Inc. (San Jose, CA)
- …but is not limited to: + Digital microarchitecture definition and documentation + RTL logic design , debug and functional verification + Strong background in ... and developing flows at all phases of the digital design and functional verification. It is further expected that...well as a thorough understanding of the end-to-end digital design flow in order to accurately and efficiently collaborate… more
- Broadcom (San Jose, CA)
- …applications. We are seeking a staff **Digital Front-End Designer** with deep expertise in RTL design , synthesis, and design optimization to drive the ... micro-architecture, and PPA trade-offs to optimize performance, power, and area. ** RTL Design and Micro-Architecture:** + Develop high-quality RTL designs… more
- Google (Mountain View, CA)
- FPGA Design Engineer , Taara Hardware Engineering Mountain View, CA About the team: Project Taarafocuses on delivering high-throughput and long-range connectivity ... feedback-based precision line-of-sight tracking systems. + Develop testbenches for RTL modules, perform simulation, and verify design ...for RTL modules, perform simulation, and verify design requirements are met. + Integrate third party IP… more
- Google (Mountain View, CA)
- …and Systems + High performance machine learning accelerator architecture, micro-architecture and RTL design . + Selection and integration of in-house and third ... can flourish. We are seeking a highly motivated Hardware Engineer to join our team and contribute to development...equivalent practical experience. + 7+ years of experience in RTL design in Verilog/System Verilog. + 5+… more
- Google (Mountain View, CA)
- …field, or equivalent practical experience. + 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog ... SystemVerilog. + Experience with logic synthesis techniques to improve RTL code, performance and power as well as low-power... code, performance and power as well as low-power design techniques. + Experience with ARM-based SoCs, interconnects and… more
- Google (Mountain View, CA)
- …field, or equivalent practical experience. + 5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog ... on computer architecture. + 10 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.… more
- Cisco (San Jose, CA)
- …contribute to chip architecture definition and discussions. * Author design specifications and participate in micro-architecture specification reviews. * Implement ... Verilog RTL to meet timing and performance requirements. * Help...performance requirements. * Help define, evolve, and support our design methodology. * Mentor junior engineers on performing project… more
- Belcan (Palo Alto, CA)
- Sr. Physical Design Engineer Job Number: 354330 Category: Design Engineering Description: Job Title: Sr. Physical Design Engineer Pay rate: $66.34 ... Keywords: #PaloAltoJobs; #PhysicalDesignEngineerjobs; Job Description: As a Sr. physical design engineer , you will contribute to all...address timing, congestion and power issues. In-Depth Knowledge of design flow from RTL to GDSII. Good… more
- Google (Mountain View, CA)
- …field, or equivalent practical experience. + 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog ... Processing Unit (CPU) front-end designs, emphasizing micro-architecture and Register Transfer Level ( RTL ) design for the next generation CPU. + Propose… more
- Cisco (San Jose, CA)
- …an ASIC Implementation Technical Lead in San Jose, CA with a primary focus on Design -for-Test. You will work with Front-end RTL teams, backend physical design ... design Team which is responsible for full Chip physical implementation from RTL to GDSII. As Physical Verification Engineer your main responsibilities will… more
- Broadcom (San Jose, CA)
- …Account, please Sign-In before you apply.** **Job Description:** **Job Description: IC Design Engineer ** + Participate in IP level architectural definition ... including micro-architecture definition + Perform RTL design using Verilog HDL, with an emphasis on performance and area + Implement multi-power and low-power… more
- Cisco (San Jose, CA)
- …Impact * Be part of the development organization as an ASIC Design Engineer with primary focus on RTL Design * Create micro-architecture specifications ... and participate in reviews * Implement Verilog RTL to meet timing and performance requirements * Help...performance requirements * Help define, evolve, and support our design methodology * Collaborate with the verification team on… more
- Cisco (San Jose, CA)
- …coverage through implementation and review of code and functional coverage. * Ensure RTL quality with qualifying the design with Gate Level Simulations on ... for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers,...is on the lookout for a driven Senior Verification Engineer to join us in developing the next generation… more
- Meta (Menlo Park, CA)
- …SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration. 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to build...development. 3. RTL development using Verilog, System Verilog and HLS. 4.… more
- Meta (Menlo Park, CA)
- …SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to build...development 3. RTL development using Verilog, System Verilog and HLS 4.… more
- Meta (Menlo Park, CA)
- …SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to build...development 3. RTL development using Verilog, System Verilog and HLS 4.… more
- Capgemini (San Francisco, CA)
- **Physical Design Engineer ** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip ... development, executing from the inception of the design ( RTL or gate netlist) through the...**Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design Engineer_ **Location:**… more
- Google (Mountain View, CA)
- …area of different design options. + Drive architectural feasibility studies, explore RTL / design tradeoffs for physical design closure. + Perform block ... can flourish. We are seeking a highly motivated Hardware Engineer to join our team and contribute to development...are willing to help out with whatever moves silicon design and architecture forward. We regularly need to invent… more
- Cisco (San Jose, CA)
- …some of the most complex ASICs being developed. Your Impact As a physical design engineer you will be spearheading the implementation of complex multi-hierarchy ... (Performance, Power, Area). * Experience and knowledge of hardware architecture and RTL /logic design for timing closure, specifically experience in critical… more
- Broadcom (San Jose, CA)
- …but not required 1. Exposure to SERDES communications protocols. 2. Logic design , chip architecture, microarchitecture, Verilog RTL coding 3. Front-end logic ... Lead for Physical Designs Are you a versatile, senior engineer capable of leading external and internal cross-functional teams?...as a resident expert in areas such as physical design , STA, DFT, and packaging? Have you taped out… more