- Arrow Electronics (San Jose, CA)
- **Position:** STA Engineer **Job Description:** POSITION SUMMARY * Proven experience in constraints (Func/Test) handling, block and top level static timing ... on Automation (Perl/Tcl/Awk/Python) * Able to provide technical guidance to Junior Engineer * Good in communication skill EDUCATION BACKGROUND A Bachelor's degree in… more
- Cisco (San Jose, CA)
- …noise, while managing ECO tasks. * Your role may include extraction and STA flow development, convergence strategies, and correlation between PNR, Spice, and STA ... practices. * Additionally, you'll develop methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive execution to… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …constraints, advanced OCV/SOCV concepts, derates, PBA timing, Distributed, Concurrent and Hierarchical STA flows. . Work efficiently with R&D and customer to enable ... basic understanding of Place and route, power analysis. Related tools/Keywords; PrimeTime, STA , Quantus #LI-MA1 The annual salary range for California is $100,100 to… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …to enable new and differentiating technologies.. + In this role, the Solutions Engineer (SE) is expected to work both independently and in collaboration with other ... team members to address customer issues and to identify new opportunities or Risk that are linked to those activities + The SE will interact with Product Engineering/RnD Team as well as Key Technologists at customer site to develop and enable new… more
- DoorDash (San Francisco, CA)
- …the foundation for decision-making at DoorDash. About the Role DoorDash is looking for a Sta ff Software Engineer ,Data to be a technical lead and help architect ... about you because + 8+ years of professional experience as a hands-on engineer and technical leader leading multiple projects + 6+ years experience working in… more
- Cisco (San Jose, CA)
- …ASICs being developed. Your Impact You are a detail-oriented Test Timing Engineer with strong analytical skills and a deep understanding of timing constraints, ... validation, CDC delay check, and SDC flow development. * STA runs, more specifically at scan modes along with...practices. * Developing methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive… more
- Cisco (San Jose, CA)
- …as a team. Your Impact You are a detail-oriented Timing Constraint (SDC) Engineer with strong analytical skills and a deep understanding of timing constraints, ... including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/ STA tools and scripting for automation, you excel at identifying and… more
- Capgemini (San Francisco, CA)
- **Physical Design Engineer ** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip development, ... top-level PnR, CTS, block integration and ECO generation. *Expertise in timing closure ( STA ) of high frequency blocks *Handling blocks of high instance counts and… more
- Capgemini (San Francisco, CA)
- **Job Title : Senior ASIC Physical Design Engineer ** **Job Location: Santa Clara, CA (Hybrid)** **Key Responsibilities** + Chip level floor planning, partitioning, ... integration and ECO generation. + Expertise in timing closure ( STA ) of high frequency blocks + Handling blocks of...towards Intelligent Industry. Capgemini Engineering has more than 55,000 engineer and scientist team members in over 30 countries… more
- Broadcom (San Jose, CA)
- …desired PPA metrics. Candidate would also be required to do equivalence checks, STA , Timing closure and power optimization. Should be able to implement timing and ... time silicon. Primary expertise in place and route and/ or timing (constraints, STA ) can be considered for this position. Candidate should extremely proficient in… more
- Broadcom (San Jose, CA)
- …timing constraint file + RTL coding, Lint checks, CDC, Synthesis, Equivalency checking, STA , RTL/gate level simulations & silicon debug + Scripting for various IC ... design tasks such as STA , equivalency checks, test bench, simulations, synthesis, etc. + prepare block level resource requirements & development schedule + generate… more
- Capgemini (San Francisco, CA)
- **Job Role:** **Physical Design (Synthesis) Engineer ** **Job Location : San Jose CA** **Job Description** + At least 7 years of experience in ASIC/SOC project design ... + Conformal LEC (Priority #1) + Synthesis tools (Synposys & Cadence) + Timing/ STA tools (PrimetimeSI & Cadence tools). **Life at Capgemini** Capgemini supports all… more
- North Wind Group (Livermore, CA)
- Job Title: Aerospace Engineer (NWS 00J07) THIS POSITION IS SHORT TERM, MAX 1000 HOURS PER CALENDAR YEAR North Wind Services is actively seeking individuals who can ... (GS) Principal Directorate's Z Program has an opening for an Aerospace Engineer to join an interdisciplinary team conducting analysis of ballistic missiles, advanced… more
- Microsoft Corporation (Mountain View, CA)
- …a difference in the world. We are looking for a **Fabric IP Design Engineer ** to join the team. **Growth Mindset** We fundamentally believe that we need a ... The Cloud Compute Development Organization is seeking a **Fabric IP Design Engineer ** to join our IP development team covering micro-architecture implementation, RTL… more
- Broadcom (San Jose, CA)
- …Broadcom's ASIC Product Division is seeking candidates for HBM/DDR/SERDES Verification Lead Engineer position at our San Jose, California Development Center. We are ... seeking a highly skilled HBM and SerDes DFT Verification Engineer to join our dynamic team. In this role,...drive innovation within the team. + Working closely with STA and DI Engineers design closure for test +… more
- Renesas (San Jose, CA)
- Senior Staff Engineer , Electrical Design Job Description + Propose, Architect, and Design RTL in Verilog for use in a Mixed Signal Integrated Circuit + Contribute ... is a must + Competence in developing design constraints for synthesis, STA and P&R hand-off + Experience with gate-level simulations, causes and implications… more
- Broadcom (San Jose, CA)
- …you apply.** **Job Description:** **Job Description:** + ASIC implementation engineer with demonstrated expertise in multiple disciplines including synthesis, design ... place and route, clock methodology, power planning and analysis, timing closure, STA , signal integrity and physical design checks. + Participate in large complex… more
- Cisco (San Jose, CA)
- …off checklist and reviews for chip tape out, including test coverage, STA . * Prior experience pre-silicon DFT implementation and verification flows, and post-silicon ... test bring up procedures. Preferred qualifications: * DFT CAD development - Test Architecture, Methodology and Infrastructure * Post silicon validation using DFT patterns. Why Cisco? #WeAreCisco, where each person is unique, but we bring our talents to work as… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …design flow. Experience with design tools such as Incisive/NCSim, Genus/Design Compiler, STA with Tempus/PrimeTime, power analysis. + Experience with Lint and CDC ... tool flows. + Exposure to some major IP and protocols, such as SERDES, PCIe and DDR4. + Self-driven. Good communication, organization, analytical, presentation and people skills. The annual salary range for California is $131,600 to $244,400. You may also be… more