- Cisco (San Jose, CA)
- …some of the most complex ASICs being developed. Your Impact You are a detail-oriented Test Timing Engineer with strong analytical skills and a deep ... understanding of timing constraints, such as clock groups, various exceptions, clock... constraints at block, sub-chip, and full-chip levels in test modes, performing quality checks such as duplicated constraints,… more
- Cisco (San Jose, CA)
- …goals, and love to win as a team. Your Impact You are a detail-oriented Timing Constraint (SDC) Engineer with strong analytical skills and a deep understanding ... Experience with block/full chip SDC development in functional and test modes. * Experience in Static Timing ...and test modes. * Experience in Static Timing Analysis and prior working experience with STA tools… more
- Cisco (San Jose, CA)
- …development - Test Architecture, Methodology and Infrastructure * Background in Test Static Timing Analysis * Past experience with Post silicon validation ... in San Jose, CA with a primary focus on Design-for- Test . You will work with Front-end RTL teams, backend...What You'll Do * Responsible for implementing the Hardware Design-for- Test (DFT) features that support ATE, in-system test… more
- Microsoft Corporation (Mountain View, CA)
- …a difference in the world. We are looking for a **Fabric IP Design Engineer ** to join the team. **Growth Mindset** We fundamentally believe that we need a ... The Cloud Compute Development Organization is seeking a **Fabric IP Design Engineer ** to join our IP development team covering micro-architecture implementation, RTL… more
- Renesas (San Jose, CA)
- Senior Staff Engineer , Electrical Design Job Description + Propose, Architect, and Design RTL in Verilog for use in a Mixed Signal Integrated Circuit + Contribute ... verification reviews + Cover digital backend design from synthesis, static timing and logic equivalent checking + Creating documentation targeting design,… more
- TrustPoint (Mountain View, CA)
- …anti-jam capabilities. The improvements will support US Government position and timing service resiliency as well as enable next-generation commercial applications ... with our microsatellite based commercial infrastructure and innovative positioning and timing services. The Position With locations outside Washington DC and in… more
- Teledyne (Mountain View, CA)
- …Electronic Warfare (EW/ECM/CIED), Industrial, Missile/UAV, Radar, Satcom, Space, and Test and Measurement. Teledyne Microwave Solutions invests heavily in research ... and emerging challenges. Teledyne Microwave Solutions is hiring a Digital Design Engineer that will be responsible for the digital design of integrated circuits… more
- Arrow Electronics (San Jose, CA)
- … Engineer **Job Description:** POSITION SUMMARY * Proven experience in constraints (Func/ Test ) handling, block and top level static timing analysis, ECO ... generation at top level, handshaking with blocks for timing /functional ECO implementation, good exposure in Synthesis for block and top level. * Experience in Power… more
- Meta (Menlo Park, CA)
- …and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro-architecture development 3. ... selection and integration 6. Collaboration with verification and emulation teams in test plan development and debug 7. Collaboration with implementation team to… more
- Meta (Menlo Park, CA)
- …and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro-architecture development 3. ... selection and integration 5. Collaboration with verification and emulation teams in test plan development and debug 6. Collaboration with implementation team to… more
- Meta (Menlo Park, CA)
- …and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration. 2. Micro-architecture development. 3. ... selection and integration. Collaboration with verification and emulation teams in test plan development and debug. 5. Collaboration with implementation team to… more
- Microsoft Corporation (Mountain View, CA)
- …and augmented reality. We are looking for a ** Senior Logic Design Engineer ** to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) ... Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), power etc. + Timing closure of high-performance digital Intellectual Property (IP) + Silicon validation +… more
- Broadcom (San Jose, CA)
- …before you apply.** **Job Description:** **Job Description: IC Design Engineer ** + Participate in IP level architectural definition including micro-architecture ... crossing issues in the design + Collaborate with verification team on test plan development, debugging, and coverage closure + Collaborate with physical design… more
- TrustPoint (Mountain View, CA)
- …anti-jam capabilities. The improvements will support US Government position and timing service resiliency as well as enable next-generation commercial applications ... Valley, TrustPoint is currently seeking a Full Time Electrical Engineer to join the team and will be responsible...and the entire engineering team to design, develop and test electrical hardware that leverages our company's proprietary satellite… more
- Sierra Nevada Corporation (Fremont, CA)
- Firmware design engineer will perform design, development, documentation, integration, test and debug of FPGA and SoC architecture for DoD systems. Firmware ... design, simulation and verification, design documentation generation, firmware integration and test . Skills required include firmware design of FPGAs and SoCs.… more
- Teradyne (San Jose, CA)
- We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, ... Teradyne's test technology ensures your device works right the first...with our customer base. We are seeking an Electrical Engineer for our Nextest division to develop and maintain… more
- Vector Atomic (Pleasanton, CA)
- …is building quantum devices for applications including GPS-free navigation and timing , geophysical exploration, and telecommunications. We are focused on delivering ... and geophysical exploration. This jack-of-all-trades role requires a skilled and flexible engineer capable of operating in a dynamic R&D environment. The ideal will… more
- Broadcom (San Jose, CA)
- …Account, please Sign-In before you apply.** **Job Description:** **R&D Staff Engineer ** The ideal candidate will have expertise in integrated-circuit process ... device fabrication and operation, device modeling and circuit design, test development and execution, device-level reliability failure mechanisms and testing,… more
- Broadcom (San Jose, CA)
- …and physical memory models + Document the design specifications, behavioral description, and timing diagrams + Specify silicon test plan and correlate silicon to ... the physical macro + Integrate characterization flow to extract timing and power information + Develop scripts to automate...DFT schemes and chip level integration + Familiar with test setups, silicon testing and debug + Proficient in… more
- Teledyne (Mountain View, CA)
- …being on a team that wins. **Job Description** We are looking to add a Digital Engineer to our team based in Mountain View, CA. This is an ideal position for someone ... reviews, and project planning . Generating technical product documentation and test plans Preferred Skills/Experience: . Firmware development in Verilog using FPGAs… more