- SpaceX (Sunnyvale, CA)
- ASIC / SOC DFT Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the ... to make this possible, with the ultimate goal of enabling human life on Mars. ASIC / SOC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …world of technology. We are looking for SoC / ASIC Digital Design Engineer with experience in Design for Test ( DFT ). An intimate knowledge and experience ... preferred. + Prior 5-15 years of professional experience in SoC / ASIC Digital Design with focus on Design... Digital Design with focus on Design for Test ( DFT ) + Should possess intimate knowledge of DFT… more
- Google (Sunnyvale, CA)
- Senior DFT Static Timing Analysis Engineer , Cloud _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving problems, and ... timing analysis and timing ECO creation, timing margins). + Experience in DFT architectures and associated test methodologies. + Experience in Tessent generated … more
- Amazon (Cupertino, CA)
- …trade-offs. Key job responsibilities - integrate multiple subsystems into top level SOC , ensure correct clock/reset/functional/ DFT signal routing - As a key ... rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies...technical field - 5+ years in RTL design for SOC - 5+ years of VLSI engineering - 5+… more
- Meta (Sunnyvale, CA)
- …click "Apply to Job" online on this web page. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run logic/physical synthesis using advanced ... work w/ designers to create waivers. 6. Perform RTL DFT analysis and improve DFT coverage for...for RTL-synthesis and PrimeTime-STA for blocks and top-level including SOC . 11. Analyze inter-block timing and create IO budgets… more
- Google (Sunnyvale, CA)
- SoC Physical Design Engineer _corporate_fare_ Google...complex SoC . + Experience with multiple-cycles of SoC in ASIC design. + Experience with ... within AI/ML-driven systems. As a System on a Chip ( SoC ) Physical Design Engineer , you will collaborate...will collaborate with Register-Transfer Level (RTL), Design for Testing ( DFT ), Floorplan, and full-chip Sign off teams. Additionally, you… more
- SpaceX (Sunnyvale, CA)
- …bus routing, sequential pipeline planning and top level design for testability ( DFT ) planning + Collaborate with chip architects, ASIC engineers, package ... Sr. Full Chip Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring… more
- Cisco (San Jose, CA)
- …number of applications are received. Meet The Team You will collaborate with ASIC design teams in the Central Hardware Group, peer Test Engineers in Silicon ... test activities. Your Impact You will be a Test Engineer in Silicon Operations focusing on the ATE test...ATE test bring-up. You will partner with the Cisco ASIC team to bring up tests, characterize units, and… more