- Broadcom (San Jose, CA)
- …PhD in Electrical Engineering or Computer Engineering with 10+ years of experience in Physical design . + Deep knowledge about industry standards in Physical ... Power-grid and high speed clock constraints and specification. + Good understanding of physical design verification methodology to debug LVS/DRC issues at the… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC Physical Design Engineer...and CMOS solid state physics + Knowledge of CMOS digital design principles, basic standard cells their ... possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our… more
- Capgemini (San Francisco, CA)
- ** Physical Design Engineer** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical ... candidate should have a high aptitude for floor-planning the design of complex digital top level and/or...PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design Engineer_ **Location:**… more
- Cisco (San Jose, CA)
- … ASIC team can provide. You will work with exceptional talent with vast ASIC design and development expertise. With Cisco being a systems company, you will ... refining design and timing constraints for seamless physical design closure. As part of this...with STA tools like PrimeTime/Tempus * Understanding of related digital design concepts (eg. clocking and async… more
- Cisco (San Jose, CA)
- …team to address design bugs and close code coverage. * Work closely with physical design team to close design timing and place-and-route issues. * ... With You will work with exceptional talent with vast ASIC design and development expertise. With Cisco...to develop innovative technology and power a more inclusive, digital future for everyone. How do we do it?… more
- Capgemini (San Francisco, CA)
- **Job Title : Senior ASIC Physical Design Engineer**... and software to support the convergence of the physical and digital worlds. Coupled with the ... US by Capgemini. **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior ASIC Physical Design Engineer_ **Location:** _CA-Santa Clara_… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is seeking an ASIC Design Engineer Intern to join our Infrastructure organization. Our servers and data centers are the foundation upon which ... Engineering or related engineering fields 11. Experience with Lint, Synthesis, Formal or Physical Design tools 12. Scripting capability with Python or Perl 13.… more
- Capgemini (San Francisco, CA)
- **Job Title: ASIC Design Verification Infrastructure Engineer (Modern Python experience is must)** **Job Location: Sunnyvale, CA (Remote work is OK)** **Job ... Description:** **Key Responsibilities:** + .Assist the design verification leads to develop software for internal solutions/generators... and software to support the convergence of the physical and digital worlds. Coupled with the… more
- Cisco (San Jose, CA)
- …focus on Design -for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements ... be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with...and post silicon validation phases with additional exposure to physical design signoff activities. What You'll Do… more
- Meta (Sunnyvale, CA)
- …**Required Skills:** ASIC Engineer Intern, Implementation Responsibilities: 1. Participate in Design Implementation, Physical Design , and Design ... **Summary:** Meta is seeking an ASIC Engineer Intern to join our Infrastructure organization....efficiently. You will have an opportunity to participate in design implementation/emulation, physical design , EDA… more
- Amazon (Cupertino, CA)
- …you - come build the future with us! Key job responsibilities * Perform physical design for Amazon's machine learning custom silicon solutions * Participate in ... various aspects of physical design : full chip floorplanning, circuit analysis,...Spice Circuit analysis - Experience with Place and Route, digital implementation - Experience with EDA tools from Synopsys… more
- Cisco (San Jose, CA)
- …basis to address design bugs and close code coverage. * Work closely with physical design team to close design timing and place-and-route issues * ... Do Be part of the development organization as an ASIC Engineering Technical Leader with primary focus on RTL... Engineering Technical Leader with primary focus on RTL Design . * Create micro-architecture specifications and participate in reviews… more
- Cisco (San Jose, CA)
- …processor architecture, Ethernet processing, digital signal processing, high-speed logic design & verification, memory designs, and physical design ... and efficient memory designs, custom library development (Standard Cell and I/O), physical design & DFT, Signal Integrity, and complexed packaging technology.… more
- Amazon (Sunnyvale, CA)
- …Ph.D degree in Electrical / Communications Engineering - 7+ years of experience in digital design - Experience with physical implementation flows Amazon is ... or related field, or equivalent experience - 5+ years of experience in digital design - Experience with products that have gone to volume production - Hands… more
- Cisco (San Jose, CA)
- …focus on Design -for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements ... be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with...and post silicon validation phases with additional exposure to physical design signoff activities. What You'll Do… more
- Cisco (San Jose, CA)
- …strategies, and correlation between PNR, Spice, and STA, along with advising the Physical Design team on best practices. * Additionally, you'll develop ... accuracy. Who you'll work with You will collaborate with ASIC Front-end and Back-end teams to understand chip architecture...refining design and timing constraints for seamless physical design closure. As part of this… more
- Meta (Sunnyvale, CA)
- …machine learning accelerators and state-of-the-art SoCs. **Required Skills:** Digital Design Engineer Responsibilities: 1. Contribute to ASIC digital ... a world-class group of researchers and engineers using your digital design skills to implement and contribute...integration and ASIC architecture 12. Knowledge of Physical Design and Low power implementation 13.… more
- Meta (Sunnyvale, CA)
- …rendering hardware accelerators and state-of-the-art SoCs. **Required Skills:** Digital Design Engineer Responsibilities: 1. Contribute to ASIC digital ... firmware, and algorithms.We are growing our Graphics & Display ASIC Design and uArchitecture team within RL...a world-class group of researchers and engineers using your digital design skills to implement and contribute… more
- Broadcom (San Jose, CA)
- … design trade-offs. You will collaborate closely with verification engineers and physical design teams to ensure functional correctness, timing closure, and ... and Timing Closure:** + Perform synthesis and work with physical design teams to achieve timing closure...or similar. + **Knowledge Areas:** + Solid understanding of digital design fundamentals such as pipelining, FSMs,… more
- Teledyne (Mountain View, CA)
- …analyzing, and summarizing development and service issues + Advanced level experience with digital and ASIC design + Advanced level experience with ... capabilities for current and emerging challenges. Teledyne Microwave Solutions is hiring a Digital Design Engineer that will be responsible for the digital… more