- Meta (Sunnyvale, CA)
- …Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our...13. 3+ Years of experience as a Front End Synthesis & Integration Engineer 14. Experience with… more
- Meta (Sunnyvale, CA)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Timing Responsibilities: 1. Develop Timing ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our...16. Experience with SOC Design Integration & Front End Implementation 17. Experience with Front End Synthesis … more
- Meta (Sunnyvale, CA)
- … ASIC engineers to build "Green" data center accelerators. **Required Skills:** ASIC Engineer Intern, Implementation Responsibilities: 1. Participate in ... **Summary:** Meta is seeking an ASIC Engineer Intern to join our...You will have an opportunity to participate in design implementation /emulation, physical design, EDA infrastructure methods, and design power… more
- Meta (Sunnyvale, CA)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Static Verification Responsibilities: 1. ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our...the DFT coverage for Stuck-at faults. 5. Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate… more
- Broadcom (San Jose, CA)
- …have a Candidate Account, please Sign-In before you apply.** **Job Description:** ASIC implementation engineer with demonstrated expertise in multiple ... Electrical Engineering or Computer Engineering and 8+ years of related ASIC implementation experience or Masters degree in Electrical Engineering or Computer… more
- SpaceX (Sunnyvale, CA)
- …world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation ). In this role, you will be ... Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering)...capabilities of the Starlink network. RESPONSIBILITIES: + Perform partition synthesis and physical implementation steps (eg … more
- Meta (Sunnyvale, CA)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure organization....We are looking for individuals with experience in backend implementation from Netlist to GDSII in low power and… more
- Meta (Sunnyvale, CA)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure organization....We are looking for individuals with experience in backend implementation from Netlist to GDSII in low power and… more
- Capgemini (San Francisco, CA)
- **Physical Design Engineer ** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip ... _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design Engineer_ **Location:** _CA-San Francisco_… more
- Meta (Menlo Park, CA)
- …complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...using Verilog, System Verilog and HLS 4. Lint, CDC, Synthesis , & Power Optimization 5. Soft and hard IP… more
- Meta (Sunnyvale, CA)
- …complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Micro-architecture development. 2. RTL ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...using Verilog, System Verilog and HLS. 3. Lint, CDC, Synthesis , & Power Optimization. 4. Soft and hard IP… more
- Meta (Menlo Park, CA)
- …complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...in test plan development and debug 6. Collaboration with implementation team to close the design on timing and… more
- Meta (Menlo Park, CA)
- …complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration. 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...in test plan development and debug. 5. Collaboration with implementation team to close the design on timing and… more
- Google (Mountain View, CA)
- …concepts, and languages such as Verilog or SystemVerilog. + Experience with logic synthesis techniques to optimize RTL code, performance and power as well as ... Engineering, or Computer Science. + Experience working with architecture, design, and implementation of digital logic using Chisel. + Knowledge of accelerators (eg,… more
- Amazon (Sunnyvale, CA)
- …RTL - Ensure quality by running and tracking results of front-end tools including: Synthesis , Lint (RTL, DFT, UPF), Power Analysis and STA - Work with pre-silicon ... - 7+ years of experience in digital design - Experience with physical implementation flows Amazon is committed to a diverse and inclusive workplace. Amazon is… more
- Cisco (San Jose, CA)
- …Engineering or Computer Science, with 5+ year minimum of hands-on experience in ASIC implementation and Physical verification. * Hands-on experience in physical ... ASICs being developed. Your Impact As a physical design engineer you will be spearheading the implementation ...Science, with 3+ year minimum of hands-on experience in ASIC implementation and Physical verification. * Experience… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Semiconductor fundamentals and Static Timing Analysis is required + Prior experience with ASIC digital implementation flows and EDA tools is required; Experience ... in the field of artificial intelligence and machine learning. Lead Application Engineer is responsible for providing pre-sales and post-sales technical support for… more
- Amazon (Cupertino, CA)
- …massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new ... Proficient in programming/scripting languages (Perl, Python, C++) - Solid understanding of ASIC physical design, and methodologies including synthesis , place and… more
- Broadcom (San Jose, CA)
- …to interact with the customer on aspects including but limited to physical synthesis , influencing RTL content and coding styles that will lend itself to seamless ... to aid in overall closure and manufacture of the ASIC with emphasis on low power, optimized area, max....architecture, design, development and verification. - Significant experience with synthesis and physical synthesis tools (Synopsys and… more
- Amazon (Cupertino, CA)
- …massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Engineer to help us trail-blaze new technologies and ... for physical design closure - Drive IO/Core block physical implementation through synthesis , floor planning, bus /...3yrs in EE/CS - 4+ years of experience in ASIC Physical Design from - RTL-to-GDSII in either 7nm,… more