- Broadcom (San Jose, CA)
- …candidate will be responsible for various key tasks in the areas of chip integration and RTL design of cutting-edge network switch/routing designs. The ... and routing ASICs and various subsystems within these chips. 2). Doing chip level integration and putting all the functional blocks, soft/hard IPs, IOs, and… more
- SpaceX (Sunnyvale, CA)
- …flows as needed to meet the overall design quality of results and chip integration requirements BASIC QUALIFICATIONS: + Bachelor's degree in electrical ... Sr. Full Chip Physical Design Engineer (Silicon Engineering)...chip floorplan reviews and identify area, interconnect, IP integration , and floorplan improvement opportunities + Perform chip… more
- Google (Sunnyvale, CA)
- …its integration within AI/ML-driven systems. As a Signal Integrity/Power Integrity Engineer , you will lead chip and package design, ensuring optimal Signal ... Signal and Power Integrity Engineer , PhD, University Graduate _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving… more
- Meta (Sunnyvale, CA)
- …definition and design of Computer Vision/Image Sensing IP. 2. Contribute to chip -level integration , verification plan development and verification. 3. Define ... static timing analysis. 4. Support the test program development, chip validation and chip life until production...8. 7+ years of experience as a Digital Design Engineer 9. Experience with top level integration … more
- Meta (Sunnyvale, CA)
- …or block level uArchitecture definition and RTL implementation 2. Contribute to chip -level integration , verification plan development and verification 3. Define ... **Summary:** As a Digital Design Engineer at Meta Reality Labs, you will work...static timing analysis 4. Support the test program development, chip validation and chip life until production… more
- Microsoft Corporation (Mountain View, CA)
- …specification, Register Transfer Level (RTL) design, synthesis/Lint/CDC/FEV and System on Chip (SOC) integration on different subsystems. Throughout the program ... that mission. We are looking for a **Senior Design Engineer ** to work in the dynamic Microsoft Artificial Intelligence...work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team. The candidate must be a… more
- Google (Sunnyvale, CA)
- Senior DFT Static Timing Analysis Engineer , Cloud _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving problems, and ... 5 years of experience in static timing (ie, full chip timing signoff ownership, constraint authoring and verification, full...with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will… more
- Microsoft Corporation (Mountain View, CA)
- …specification, Register Transfer Level (RTL) design, synthesis/Lint/CDC/FEV and System on Chip (SOC) integration on different subsystems. Throughout the program ... that mission. We are looking for a Senior Design Engineer to work in the dynamic Microsoft Artificial Intelligence...work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team. The candidate must be a… more
- Broadcom (San Jose, CA)
- …technologies, such as co-packaged fiber-optic transceivers and connectors and complex chip stacking (3DIC, hybrid copper bonding, heterogeneous integration , ... **Job Description:** Broadcom is seeking an experienced package mechanical FEA engineer for very-large and complex packages for industry-leading ASICs. You will… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …impact on the world of technology. We are seeking a highly skilled Design Engineer to join our Palladium Solutions Development team, to drive the development of ... developing and integrating and validating high speed interface [Serdes, Chip 2 chip link] based subsystems in...circuits in analog Mixed Signal Designs and components (PHYs). Integration includes the PHY, Controller / Mac and the… more
- Microsoft Corporation (Mountain View, CA)
- …and partners worldwide and we are looking for a **Principal Physical Design Engineer ** to help achieve that mission. As Microsoft's cloud business continues to grow ... hardware. We are looking for a Principal Physical Design Engineer for customer focused solutions, insight and industry knowledge...will be responsible for Physical Design tasks at block, sub- chip , and/or full- chip level. The tasks will… more
- Meta (Sunnyvale, CA)
- **Summary:** We are looking for a Digital Design Engineer to support our Reality Labs Silicon AI Research team. We build research silicon to demonstrate and ... next generation AI and AR solutions.As a Digital Design Engineer (DDE), you will be a key contributor in...enable you to contribute to all phases of the chip development. Additionally, effective collaboration and communication with Digital… more
- Google (Sunnyvale, CA)
- …and its integration within AI/ML-driven systems. As a System on a Chip (SoC) Physical Design Engineer , you will collaborate with Register-Transfer Level ... SoC Physical Design Engineer _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid**...layout verification and design rules. + Experience in IP integration (eg, memories, IO's and Analog IP) with the… more
- Teradyne (San Jose, CA)
- …team is looking for a highly motivated, energetic and driven Field Application Engineer in ATE (Automated Test Equipment) and SLT (System Level Testing), who will ... solutions on ATE for Digital, High-Speed Digital, System on Chip , Mixed Signal and Analog semiconductor devices. + Develop...devices. + Develop knowledge and expertise on SLT system integration . + Test program software development, often done in… more
- Cisco (San Jose, CA)
- **Sr. ASIC Engineer ** The application window is expected to close on 1/26/2026. The job posting may be removed earlier if the position is filled or if a sufficient ... to first customer shipments. **Your Impact** You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints,… more
- Google (Sunnyvale, CA)
- Hardware Architecture Modeling Engineer , PhD, University Graduate _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving ... complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a Hardware Architecture Modeling Engineer ,… more
- Google (San Francisco, CA)
- Mechanical Engineer , Cooling System, Google Data Centers _corporate_fare_ Google _place_ Austin, TX, USA; Kirkland, WA, USA; +5 more; +4 more **Advanced** Experience ... environment, collaborating with cross-functional teams to design, analyze, and optimize chip -to-chiller cooling systems. Behind everything our users see online is… more
- Google (Sunnyvale, CA)
- Senior ASIC Power Engineer , ML Accelerators _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving problems, and mentoring ... an emphasis on computer architecture. + Experience defining and implementing chip -wide power management architectures and designs. + Experience in power modeling,… more
- Meta (Sunnyvale, CA)
- …to GDSII in low power and high-performance designs to build efficient System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer ... and drive execution 3. Deliver physical design of an end-to-end IP or integration of ASIC/SoC design and point out lower power and higher performance trade-offs… more
- Amazon (Cupertino, CA)
- …resources here to help you develop into a better-rounded professional. Custom SoCs (System on Chip ) live at the heart of AWS Machine Learning servers. As a member of ... world-class server infrastructure; we're handling massive scale and rapid integration of emergent technologies. We're looking for an ASIC...Curious" mindset About the team Custom SoCs (System on Chip ) live at the heart of AWS Machine Learning… more