- Broadcom (San Jose, CA)
- …San Jose, California Development Center. We are seeking a highly skilled HBM and SerDes DFT Verification Engineer to join our dynamic team. In this role, you ... our HBM, DDR and SerDes designs through comprehensive Design for Test ( DFT ) verification strategies. You will work collaboratively with cross-functional teams to… more
- Meta (Sunnyvale, CA)
- …DFT EDA tools and IEEE standards (1149, 1500, 1687). **Required Skills:** ASIC Engineer , DFT Responsibilities: 1. Develop and implement DFT strategies for ... **Summary:** Meta is hiring ASIC DFT Engineers within our Infrastructure organization to work...our Infrastructure organization to work on Design for Test ( DFT ) methodologies, implementation, and verification to build best-in-class System… more
- Cisco (San Jose, CA)
- …Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you ... groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon… more
- Broadcom (San Jose, CA)
- …you apply.** **Job Description:** Broadcom's CSG division is seeking candidate for a DFT lead position. The successful candidate will be responsible for leading most ... network switching ASIC DFx (Design for Test/debug & manufacturability) from DFT architecture, to implementation, verification, timing closure, ATE pattern bringup. .… more
- Google (Sunnyvale, CA)
- …product engineering. + Experience in Application-Specific Integrated Circuit (ASIC) or SoC DFT test development, bring-up, or debug for NPI prototypes or High Volume ... cross-functional teams. + Own IP-level test development for Design for testing ( DFT ) structural tests, functional tests, or eFuse programming. + Support Chip-level … more
- SpaceX (Sunnyvale, CA)
- Sr. DDR IP Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out exploring the stars ... enabling human life on Mars. SR. DDR IP DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience...crossing (CDC) logic + Exposure to Design For Test ( DFT ), understanding of scan and writing DFT … more
- Abbott (Alameda, CA)
- …Our location in Alameda, CA currently has an opportunity for a Senior Electrical Engineer and this is a full time in-office role. This individual will work ... using Altium design tools. Anticipate and resolve DFM and DFT issues. + Develop product specifications, design FMEAs, and...using Altium design tool, EMC design for compliance, DFM, DFT , Agile PLM tool + Design requirement management tools… more
- Broadcom (San Jose, CA)
- …Description:** Technical Lead for Physical Designs Are you a versatile, senior engineer capable of leading external and internal cross-functional teams? Do your ... resident expert in areas such as physical design, STA, DFT , and packaging? Have you taped out so many...logic design verification, DRC, logic synthesis 4. Knowledge of DFT methods including scan, boundary scan, memory BIST and… more
- Cisco (San Jose, CA)
- …Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you ... networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow...physical implementation from RTL to GDSII. As Physical Verification Engineer your main responsibilities will include: * Perform full… more
- Amazon (Sunnyvale, CA)
- …the world. Come work at Amazon! The Role: As Senior Silicon ATE Test Engineer , you will engage with an experienced cross-disciplinary staff to conceive and design ... SoCs tested on Teradyne and Advantest equipment. Convert test patterns from the DFT team into tester-suitable formats (eg ATP). Run test vectors on test platforms… more
- Cisco (San Jose, CA)
- …designs, custom library development (Standard Cell and I/O), physical design & DFT , Signal Integrity, and complexed packaging technology. Our silicon is developed ... processing, high-speed logic design & verification, memory designs, and physical design & DFT . Why Cisco #WeAreCisco, where each person is unique, but we bring our… more
- Capgemini (San Francisco, CA)
- **Job Role:** **Physical Design (Synthesis) Engineer ** **Job Location : San Jose CA** **Job Description** + At least 7 years of experience in ASIC/SOC project design ... and development + Hands on with Cadence tools, DFT flow & physical aware flow + Prior experience...towards Intelligent Industry. Capgemini Engineering has more than 55,000 engineer and scientist team members in over 30 countries… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out exploring ... goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets… more
- Meta (Sunnyvale, CA)
- …Silicon Lifecycle, to build and scale silicon for data center applications.As an ASIC Engineer in the Infra Silicon Characterization team, you will be part of a ... ASIC solutions for Meta's data center applications. **Required Skills:** ASIC Engineer - Infra Silicon Characterization Responsibilities: 1. Work across all aspects… more
- Snap Inc. (Palo Alto, CA)
- …+ Experience routing impedance controlled nets, including differential pairs, per engineer 's instructions and component specifications. + Strong skills in designing ... Design for Manufacturability (DFM), Design for Assembly (DFA), and Design for Testability ( DFT ) + Knowledge of PCB design standards for common interfaces in consumer… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …sales/marketing career opportunities, the skills and expertise you gain as an Application Engineer here at Cadence will put you miles ahead in your career ... with IC digital implementation flows and font-end EDA tools including Synthesis, DFT , and Logical Equivalence CheckingPrior experience with Cadence tools such as… more
- Insight Global (San Jose, CA)
- Job Description Insight Global is seeking a experienced Test Engineer to join a large networking company in the Bay Area. You will be joining the Silicon Operations ... will have experience in development and debug to provide insights to production and DFT . Salary expectations for this role range from $25-28/hour We are a company… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …excited to welcome highly talented hardware design leaders/managers and application engineer leaders/managers to join our Cadence North America Field Applications ... with IC digital implementation flows and font-end EDA tools including Synthesis, DFT , and Logical Equivalence Checking + Prior experience with Cadence tools such… more
- Teradyne (San Jose, CA)
- …succeed within an open collaborative peer environment. As a Hardware Test Engineer you will be responsible for defining and implementing manufacturing test strategy ... coverage to ensure products are built free of manufacturing defects. + Understanding of DFT (Design for Test) and DFM (Design for Manufacturing) method a plus +… more
- Power Integrations (San Jose, CA)
- Senior Test Engineer Location: San Jose, CA, United States Type of Employee: Full Time Job Description: + Designs develops and implements cost-effective testing ... products. + Work with IC design team to understand design specifications and DFT proposals. + Create test programs in C language, debug and validate silicon… more