• Design Verification ( DV

    Cisco (San Jose, CA)
    …and Verification teams and Architects to understand chip architecture and drive design verification requirements. You'll work with SDK and Software teams as ... ASIC in deployment-mode applications * You will participate in the ASIC design verification and Emulation for Cisco high-end switching products. One of the… more
    Cisco (01/24/25)
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  • Senior Design Verification

    Cisco (San Jose, CA)
    …developed in the industry. What You'll Do You will participate in the ASIC design verification and Emulation for Cisco high-end switching products. One of the ... Verification teams and Architects to understand chip architecture and drive design verification requirements. You'll work with SDK and Software teams as part… more
    Cisco (01/07/25)
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  • ASIC Design Verification

    Cisco (San Jose, CA)
    …You Are The Core Hardware Business Unit is on the lookout for a driven Senior Verification Engineer to join us in developing the next generation of Silicon One ... Specific responsibilities include: * Architect block, cluster and top-level DV environment infrastructure. * Develop DV infrastructure...other related field. * 7+ years of related ASIC design verification experience. * Proficient in ASIC… more
    Cisco (12/31/24)
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  • ASIC Design Verification

    Capgemini (San Francisco, CA)
    …US by Capgemini. **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _ASIC Design Verification Engineer (with modern Python programming)_ ... **Job Title: ASIC Design Verification Infrastructure Engineer ...to develop software for internal solutions/generators to support SoC DV and Firmware engineers. + .Support existing DV more
    Capgemini (01/03/25)
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  • Senior Mixed-Signal Design

    Google (Mountain View, CA)
    verification using SystemVerilog for ASIC designs. + Experience developing and maintaining design verification ( DV ) testbenches, test cases, and test ... for cross-functional teams and lead or drive the building of reusable design verification ( DV ) infrastructure components. Google is proud to be an equal… more
    Google (01/15/25)
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  • ASIC Engineer , Design

    Meta (Sunnyvale, CA)
    **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. As a Design Verification Engineer , you will ... towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1....7. Experience in verifying a IP block using standard DV based techniques. 8. Experience in EDA tools and… more
    Meta (01/25/25)
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  • ASIC Design Verification

    Cisco (San Jose, CA)
    …Work With: You will be in the Silicon One development organization as an ASIC design verification engineer in San Jose, CA. You collaborate closely with ... for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers... verification engineers, designers, hardware and cross-functional teams to verify… more
    Cisco (11/01/24)
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  • FPGA Verification Engineer , Kuiper…

    Amazon (Sunnyvale, CA)
    …to contribute to a groundbreaking new system with few legacy constraints. The FPGA verification engineer will work with design and systems teams to ... Enhance your leadership skills while contributing to a dynamic DV team * Create reusable Verification IP...verification simulation solutions. The FPGA verification engineer will work with FPGA design and… more
    Amazon (01/04/25)
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  • Senior ASIC Design Verification

    Cisco (San Jose, CA)
    …customer shipments. What You'll Do * You will participate in the ASIC design verification for Cisco high-end switching products. * Development of simulation ... with outstanding talent and vast ASIC development expertise in design , DV , DFT, physical design ,...* Experience in System Verilog/UVM. * Experience with ASIC design and verification processes, debugging, methodology, and… more
    Cisco (01/24/25)
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  • ASIC Design Verification

    Cisco (San Jose, CA)
    …Degree in EE, CE, or other related field. * 5+ years of related ASIC design verification experience. * Proficient in ASIC verification using UVM/System ... hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers, the Public… more
    Cisco (01/10/25)
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  • ASIC Verification Engineer

    Cisco (San Jose, CA)
    …of the most complex ASICs being developed in the industry. Your Impact As ASIC Verification Engineer in The Core Hardware Business Unit, you will be engaged the ... infrastructure for block, cluster and top level environments. *Maintaining existing DV environments and enhancing them *Ensuring complete verification coverage… more
    Cisco (01/24/25)
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  • Director - Design Verification

    Microsoft Corporation (Mountain View, CA)
    …and artificial intelligence at scale. We are looking for a **Director - Design Verification ** to work in the dynamic Microsoft Artificial Intelligence Silicon ... Engineering (AISiE) SoC Design Verification team. The candidate will be...thrive at work and beyond. **Responsibilities** The AISiE SoC DV team is seeking a passionate, driven, and intellectually… more
    Microsoft Corporation (01/17/25)
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  • ASIC Implementation Engineer - Static…

    Meta (Sunnyvale, CA)
    …(SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Static Verification Responsibilities: 1. Perform Flat and ... including (Lint, CDC, RDC,). 7. Work closely with the Design Engineers, DV Engineers, Emulation Engineers in...practical experience. 9. 5+ years of experience in static verification tools 10. Experience with Lint, Clock Domain &… more
    Meta (01/23/25)
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  • ASIC Engineer

    Cisco (San Jose, CA)
    …What You'll Do The Core Hardware Business Unit is looking for a motivated Senior Verification engineer /lead to engage in new development of our UCS family. You ... DV environments and enhancing them * Ensuring complete verification coverage through implementation and review of code and...ASIC bring up Minimum Qualifications * 8+ years ASIC design verification experience with Bachelor's or Master's… more
    Cisco (12/31/24)
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  • ASIC Implementation Engineer - Synthesis

    Meta (Sunnyvale, CA)
    …including (Lint, CDC, RDC, Synthesis, STA, Power). 10. Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the ... Level and identify power reduction opportunities. 4. Run Formal Verification checks between RTL and Gate level netlist and...of experience as a Front End Synthesis & Integration Engineer 14. Experience with RTL Synthesis and design more
    Meta (01/23/25)
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  • Senior Embedded Software Engineer

    Capgemini (San Francisco, CA)
    **Job description:** We are seeking a highly seasoned Lead Embedded Software Engineer to join our dynamic team. In this role, we will lead and develop, compile, run, ... power tests and evaluation on prototyping platforms. Android development experience . DV experience of developing tests at complex Subsystem or SOC level… more
    Capgemini (10/29/24)
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  • Emulation and Silicon Validation Engineer

    Broadcom (San Jose, CA)
    …efficiency, reusability, and value. + **Reusable Components:** Create reusable synthesizable design blocks, libraries, and verification components to streamline ... global user community. + **Cross-functional Collaboration:** Collaborate with Architecture, Micro-Architecture, Design , DV , Software, and other teams to achieve… more
    Broadcom (11/27/24)
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  • Senior Embedded Software Engineer

    Capgemini (San Francisco, CA)
    …in power tests and evaluation on prototyping platforms Android development experience DV experience of developing tests at complex Subsystem or SOC level ... their journey towards Intelligent Industry. Capgemini Engineering has more than 55,000 engineer and scientist team members in over 30 countries across sectors… more
    Capgemini (01/23/25)
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  • Infrastructure Tools and Methodology Lead

    Google (Sunnyvale, CA)
    …planning and deploying new tools and flows to users. + Knowledge of chip design process, either verification , design or implementation. + Ability to ... delivering unparalleled performance, efficiency, and integration. As a Hardware Engineer , you will design and build the...teams to influence and standardize methodology across functional areas ( Design , DV , PD). + Perform or guide… more
    Google (01/17/25)
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