- Amazon (Cupertino, CA)
- …massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze ... 10yrs or MS + 7yrs in EE/CS - 5+ years of experience in developing physical design methodology or CAD flows in synthesis, PNR, and sign-off areas for… more
- quadric.io, Inc (Burlingame, CA)
- …Happiness What We Expect: Initiative, Collaboration, Completion Role As a member of our physical design methodology team you will be tasked with developing ... physical design methodologies and automation scripts for multiple design configurations across multiple process nodes. Responsibilities + Develop Quadric… more
- Belcan (Palo Alto, CA)
- Sr. Physical Design Engineer Job Number: 354330 Category: Design Engineering Description: Job Title: Sr. Physical Design Engineer Pay rate: ... Start Date: Right Away Keywords: #PaloAltoJobs; #PhysicalDesignEngineerjobs; Job Description: As a Sr. physical design engineer , you will contribute to all … more
- Capgemini (San Francisco, CA)
- ** Physical Design Engineer ** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical ... **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design Engineer_ **Location:** _CA-San… more
- Meta (Sunnyvale, CA)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure...data-path intensive designs. 24. Experience in the 3D-IC technology, methodology , and advanced packaging. 25. Experience in validating Power… more
- Capgemini (San Francisco, CA)
- **Job Title : Senior ASIC Physical Design Engineer ** **Job Location: Santa Clara, CA (Hybrid)** **Key Responsibilities** + Chip level floor planning, ... **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior ASIC Physical Design Engineer_ **Location:** _CA-Santa Clara_ **Requisition ID:**… more
- Broadcom (San Jose, CA)
- …features as well as manage extremely large volumes of internet traffic. As a Senior Physical Design Engineer , the ideal candidate will be responsible for the ... signal and power EM checks. . Methodology & Flow development of Physical Design and Timing Closure. . Interfacing with internal and external teams including … more
- Broadcom (San Jose, CA)
- … methodology , power planning and analysis, timing closure, signal integrity and physical design checks. Participate in large complex design ... you apply.** **Job Description:** Broadcom is lookign for ASIC implementation engineer with demonstrated expertise in multiple disciplines including synthesis, … more
- Broadcom (San Jose, CA)
- …Power-grid and high speed clock constraints and specification. + Good understanding of physical design verification methodology to debug LVS/DRC issues at ... in Electrical Engineering or Computer Engineering with 10+ years of experience in Physical design . + Deep knowledge about industry standards in Physical … more
- Microsoft Corporation (Mountain View, CA)
- …SOCs, cloud accelerators, cloud servers, and clients. We are looking for a Senior Design Verification Engineer to work on leading edge IP (intellectual property) ... work and beyond. We are looking for a **Senior Design Verification Engineer ** to join the team....random stimulus, scoreboards and checkers, and assertions to verify design correctness. + Develop Universal Verification Methodology … more
- Jacobs (San Francisco, CA)
- …up our communities today to improve tomorrow. We're looking for a mid-level Engineer to design geotechnical aspects of environmental remedial actions for complex ... pass your knowledge on to others. As a junior/mid-level Engineer , you'll be directed by Design Managers...field work for remediation projects, and an understanding of methodology and procedures * Experience working on active project… more
- Meta (Sunnyvale, CA)
- **Summary:** Join Meta's Wearable Silicon AMS team as a Digital Mixed Signal Design Engineer and work alongside world-class researchers and engineers to develop ... and augmented reality systems. **Required Skills:** Digital Mixed Signal Design Engineer Responsibilities: 1. Collaborate with AMS...constraints, UPF files, and other collateral for hand-off to physical design 6. Perform RTL power analysis… more
- Cisco (San Jose, CA)
- …hardware solutions. Your Impact * Be part of the development organization as an ASIC Design Engineer with primary focus on RTL Design * Create ... performance requirements * Help define, evolve, and support our design methodology * Collaborate with the verification...bugs and close code coverage * Work closely with physical design team to close design… more
- Cisco (San Jose, CA)
- …* Develop and analyze functional coverage. * Help define, evolve, and support our design methodology . * Collaborate with the verification team to address ... design bugs and close code coverage. * Work closely with the physical design team to close design timing and place-and-route issues. * Triage, debug, and… more
- Google (Mountain View, CA)
- …dependencies and deliverables. + Work closely with system, software, design , Design for testing (DFT) and physical implementation stakeholders to make ... using SystemVerilog for ASIC designs. + Experience developing and maintaining design verification (DV) testbenches, test cases, and test environments. Preferred… more
- Cisco (San Jose, CA)
- …to meet timing and performance requirements. * Help define, evolve, and support our design methodology . * Mentor junior engineers on performing project tasks and ... address design bugs and close code coverage. * Work closely with physical design team to close design timing and place-and-route issues. * Triage, debug,… more
- Cisco (San Jose, CA)
- …Work With You will work with outstanding talent and vast ASIC development expertise in design , DV, DFT, physical design , and post-silicon validation The team ... related experience * Experience in System Verilog/UVM. * Experience with ASIC design and verification processes, debugging, methodology , and tools. * Experience… more
- Motion Recruitment Partners (Palo Alto, CA)
- Senior Hardware Engineer Palo Alto, CA **Onsite** Contract $70/hr - $75/hr Physical Design Engineer As a Physical Design Engineer , you will ... contribute to all design phases of physical design of high performance SoC ...to GDSII. You will collaborate with the Foundry Process Engineer , SoC Architect, Microarchitecture, Packaging, Signal Integrity and Power… more
- Meta (Sunnyvale, CA)
- …Engineers in supporting them with the handoff tasks. 11. Interact with Physical Design Engineers and provide them with timing/congestion feedback. **Minimum ... in SOC Design Integration and Front-End Implementation. 20. Knowledge of Physical Design flow such as Floorplanning, CTS, Routing 21. Good Understanding… more
- TE Connectivity (San Francisco, CA)
- Principal Signal Integrity Engineer - Data & Devices At TE, you will unleash your potential working with people from diverse backgrounds and industries to create a ... sustainable and more connected world. **Job Overview** As a Principal Signal Integrity Engineer for TE Connectivity you will focus on the electrical design ,… more