• RTL Design Engineer

    Capgemini (San Francisco, CA)
    ** RTL Design Engineer ** **Location: San Jose CA / Bay Area, but will consider remote.** **Job description:** . As an RTL Design Engineer you will ... . Develop micro architectural document from requirements specifications. . Extensive RTL design utilizing Verilog / SystemVerilog . Perform basic… more
    Capgemini (10/12/24)
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  • TPU Compute RTL Design

    Google (Sunnyvale, CA)
    …delivering unparalleled performance, efficiency, and integration. As a Tensor Processing Unit (TPU) Compute RTL Design Engineer you will be part of a team ... Work with Design Validation (DV) teams to create testplans to verify and debug design RTL . + Work with physical design teams to ensure design meets… more
    Google (12/27/24)
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  • ASIC Rtl Design Engineer

    Broadcom (San Jose, CA)
    …We are seeking for an experienced RTL Designer for our team. The engineer will be responsible for design & development of digital circuits including defining ... Science and 8+ years of meaningful experience in SOC architecture and design experience or Master's Degree in Electrical Engineering, Computer Engineering, or… more
    Broadcom (11/01/24)
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  • DSP or Serdes (Viterbi and encoder design

    Cadence Design Systems, Inc. (San Jose, CA)
    …but is not limited to: + Digital microarchitecture definition and documentation + RTL logic design , debug and functional verification + IP integration and ... and developing flows at all phases of the digital design and functional verification. It is further expected that...on DSP or High Speed Serdes (Viterbi and encoder design ). . The ideal candidate will have at least… more
    Cadence Design Systems, Inc. (01/04/25)
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  • ASIC Rtl Engineer Intern, Annapurna…

    Amazon (Cupertino, CA)
    …for in the United States. In Annapurna Labs we are at the forefront of hardware co- design not just in Amazon Web Services (AWS) but across the industry. The work we ... while also being deeply important to our customers. We design and build every component of our hardware and...the future with us! Responsibilities: * Participate in logic design activities as part of Amazon's machine learning custom… more
    Amazon (11/16/24)
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  • SoC Design Engineer , Google Cloud

    Google (Sunnyvale, CA)
    …efficiency, and integration. In this role, you will join a team working on SoC-level RTL design for our data center accelerators. You'll own RTL , ... segmentation to enable programmatic assembly of custom solutions based off user design intent. + Design RTL architecture of system to allow for automated… more
    Google (12/20/24)
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  • Digital Design Engineer

    Broadcom (San Jose, CA)
    …applications. We are seeking a staff **Digital Front-End Designer** with deep expertise in RTL design , synthesis, and design optimization to drive the ... micro-architecture, and PPA trade-offs to optimize performance, power, and area. ** RTL Design and Micro-Architecture:** + Develop high-quality RTL designs… more
    Broadcom (12/18/24)
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  • FPGA Design Engineer , Taara

    Google (Mountain View, CA)
    FPGA Design Engineer , Taara Hardware Engineering Mountain View, CA About the team: Project Taarafocuses on delivering high-throughput and long-range connectivity ... feedback-based precision line-of-sight tracking systems. + Develop testbenches for RTL modules, perform simulation, and verify design ...for RTL modules, perform simulation, and verify design requirements are met. + Integrate third party IP… more
    Google (10/31/24)
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  • ASIC Design Engineer , Cloud-Scale…

    Amazon (Cupertino, CA)
    …Basic Qualifications - BS in Electrical Engineering or related technical field - 5+ years in RTL design for SOC - 5+ years in VLSI engineering - 5+ years with ... will implement and deliver high performance, area and power efficient RTL to achieve design targets and specifications. - Analyze design , microarchitecture… more
    Amazon (12/19/24)
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  • ASIC Design Engineer , Platform IP,…

    Google (Mountain View, CA)
    …field, or equivalent practical experience. + 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog ... SystemVerilog. + Experience with logic synthesis techniques to improve RTL code, performance and power as well as low-power... code, performance and power as well as low-power design techniques. + Experience with ARM-based SoCs, interconnects and… more
    Google (12/10/24)
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  • Sr. DDR IP Design Engineer (Silicon…

    SpaceX (Sunnyvale, CA)
    Sr. DDR IP Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out exploring the ... of enabling human life on Mars. SR. DDR IP DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're...Controller/PHY IP core development and integration + Responsible for RTL design , synthesis, timing constraints, power estimation,… more
    SpaceX (10/21/24)
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  • Senior Silicon Digital Design

    Google (Mountain View, CA)
    …field, or equivalent practical experience. + 5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog ... on computer architecture. + 10 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.… more
    Google (12/10/24)
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  • SoC UPF Design Engineer , Google…

    Google (Sunnyvale, CA)
    …efficiency, and integration. In this role, you will join a team working on SoC-level RTL design for our data center accelerators. In this role you will own ... top-level RTL , architecture, design and implementation of global communication busses, and integration of complex ASIC designs. This is a cross-functional and… more
    Google (12/18/24)
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  • Physical Design Engineer , Annapurna…

    Amazon (Cupertino, CA)
    …and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Engineer to help us trail-blaze new technologies and architectures, ... like team through excellent collaboration and teamwork with other physical design engineers as well as with the RTL /Arch. teams A day in the life About the team… more
    Amazon (11/01/24)
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  • Senior Silicon Design Engineer

    Microsoft Corporation (Mountain View, CA)
    …cloud servers, clients, and augmented reality. We are looking for a **Senior** **Silicon** ** Design Engineer ** to work on leading edge custom IP development as ... responsible for leading the microarchitecture and Register Transfer Level ( RTL ) implementation of custom IP blocks, working with a...custom IP blocks, working with a group of other design team members, design verification engineers, and… more
    Microsoft Corporation (12/18/24)
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  • FPGA Design Engineer

    Meta (Sunnyvale, CA)
    …our tools and processes from each project to the next. **Required Skills:** FPGA Design Engineer Responsibilities: 1. Drive RTL development and testing for ... with the ones they love most. As a FPGA Design Engineer within the multidisciplinary Metaverse Prototyping...or equivalent experience 10. 8+ years of end-to-end FPGA design experience ( RTL , Simulation, Implementation, Hands on… more
    Meta (01/07/25)
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  • Silicon Digital Design Engineer III

    Google (Mountain View, CA)
    …field, or equivalent practical experience. + 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog ... SystemVerilog. + Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power... code, performance and power as well as low-power design techniques. Preferred qualifications: + Master's degree or PhD… more
    Google (12/07/24)
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  • CPU Register Transfer Level Design

    Google (Mountain View, CA)
    …field, or equivalent practical experience. + 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog ... Processing Unit (CPU) front-end designs, emphasizing micro-architecture and Register Transfer Level ( RTL ) design for the next generation CPU. + Propose… more
    Google (12/14/24)
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  • Digital Mixed Signal Design Engineer

    Meta (Sunnyvale, CA)
    **Summary:** Join Meta's Wearable Silicon AMS team as a Digital Mixed Signal Design Engineer and work alongside world-class researchers and engineers to develop ... and augmented reality systems. **Required Skills:** Digital Mixed Signal Design Engineer Responsibilities: 1. Collaborate with AMS...UPF files, and other collateral for hand-off to physical design 6. Perform RTL power analysis and… more
    Meta (01/02/25)
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  • Principal SoC Design Engineer

    Microsoft Corporation (Mountain View, CA)
    …cloud servers, clients, and augmented reality. We are looking for a Principal SOC Design Engineer to work in the dynamic Microsoft Artificial Intelligence System ... everyone can thrive at work and beyond. We are looking for a **Principal SoC Design Engineer ** to join our team! **Responsibilities** + Contribute to the SoC … more
    Microsoft Corporation (12/20/24)
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