- Arrow Electronics (San Jose, CA)
- **Position:** STA Engineer **Job Description:** POSITION SUMMARY * Proven experience in constraints (Func/Test) handling, block and top level static timing ... on Automation (Perl/Tcl/Awk/Python) * Able to provide technical guidance to Junior Engineer * Good in communication skill EDUCATION BACKGROUND A Bachelor's degree in… more
- Cisco (San Jose, CA)
- …and noise, while managing ECO tasks. *Your role may include extraction and STA flow development, convergence strategies, and correlation between PNR, Spice, and ... STA , along with advising the Physical Design team on...*Additionally, you'll develop methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive… more
- DoorDash (San Francisco, CA)
- …the foundation for decision-making at DoorDash. About the Role DoorDash is looking for a Sta ff Software Engineer ,Data to be a technical lead and help architect ... about you because + 8+ years of professional experience as a hands-on engineer and technical leader leading multiple projects + 6+ years experience working in… more
- Cisco (San Jose, CA)
- …ASICs being developed. Your Impact You are a detail-oriented Test Timing Engineer with strong analytical skills and a deep understanding of timing constraints, ... validation, CDC delay check, and SDC flow development. * STA runs, more specifically at scan modes along with...practices. * Developing methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive… more
- Meta (Sunnyvale, CA)
- …and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Timing Responsibilities: 1. Develop Timing Constraints for RTL-Synthesis and ... PrimeTime- STA for the blocks and the top-level including SOC....Hierarchical Constraints for Functional & DFT Modes. 4. Perform STA for full chip and Physical partition blocks using… more
- Meta (Sunnyvale, CA)
- …and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical Synthesis using advanced ... DFT coverage for Stuck-at faults. 7. Develop Timing Constraints for RTL-Synthesis and PrimeTime- STA for the blocks and the top-level including SOC. 8. Analyze the… more
- Belcan (Palo Alto, CA)
- Sr. Physical Design Engineer Job Number: 354330 Category: Design Engineering Description: Job Title: Sr. Physical Design Engineer Pay rate: $66.34 /hr. Location: ... Keywords: #PaloAltoJobs; #PhysicalDesignEngineerjobs; Job Description: As a Sr. physical design engineer , you will contribute to all design phases of physical design… more
- Capgemini (San Francisco, CA)
- **Physical Design Engineer ** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip development, ... top-level PnR, CTS, block integration and ECO generation. *Expertise in timing closure ( STA ) of high frequency blocks *Handling blocks of high instance counts and… more
- Motion Recruitment Partners (Palo Alto, CA)
- Senior Hardware Engineer Palo Alto, CA **Onsite** Contract $70/hr - $75/hr Physical Design Engineer As a Physical Design Engineer , you will contribute to all ... from RTL to GDSII. You will collaborate with the Foundry Process Engineer , SoC Architect, Microarchitecture, Packaging, Signal Integrity and Power Integrity teams to… more
- Google (Mountain View, CA)
- …ambitious research can flourish. We are seeking a highly motivated Hardware Engineer to join our team and contribute to development of groundbreaking silicon ... a must. The Role: We are seeking a talented and highly motivated hardware engineer to join our GenAI technical infrastructure research hardware team. You will have… more
- Broadcom (San Jose, CA)
- …Description:** Technical Lead for Physical Designs Are you a versatile, senior engineer capable of leading external and internal cross-functional teams? Do your ... a resident expert in areas such as physical design, STA , DFT, and packaging? Have you taped out so...power management. 4. Hands-on experience in physical design and STA 5. Well verse in EDA tools for physical… more
- Amazon (Cupertino, CA)
- …of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and architectures, while ensuring ... physical design, and methodologies including synthesis, place and route, STA , IR, formal and physical verification. - Demonstrated level...in PD tools such as Innovus, ICC2, Fusion Compiler, STA , and Sign-Off. - Proven track record of delivering… more
- Google (Sunnyvale, CA)
- …cross-functional teams, including chip top design, physical design, Static Timing Analysis ( STA ), package, and system teams. + Experience with 2.5D/3D package design ... (eg, silicon interposer, silicon bridge, 3D die stacking, STA , Voltage budget). + Expertise in signal and power integrity for various high speed interconnects (eg,… more
- Capgemini (San Francisco, CA)
- **Job Title: RTL Engineer ** **Job Location:** **San Francisco CA** **Job Description** We are seeking Digital Design/RTL Design engineer for our Full Time ... crafting timing constraint file, and work closely with Synthesis, STA , PD and DFT teams to meet all functional...towards Intelligent Industry. Capgemini Engineering has more than 55,000 engineer and scientist team members in over 30 countries… more
- Capgemini (San Francisco, CA)
- **Job Role:** **Physical Design (Synthesis) Engineer ** **Job Location : San Jose CA** **Job Description** + At least 7 years of experience in ASIC/SOC project design ... + Conformal LEC (Priority #1) + Synthesis tools (Synposys & Cadence) + Timing/ STA tools (PrimetimeSI & Cadence tools). **Life at Capgemini** Capgemini supports all… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out exploring ... goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets… more
- Broadcom (San Jose, CA)
- …Broadcom's ASIC Product Division is seeking candidates for HBM/DDR/SERDES Verification Lead Engineer position at our San Jose, California Development Center. We are ... seeking a highly skilled HBM and SerDes DFT Verification Engineer to join our dynamic team. In this role,...drive innovation within the team. + Working closely with STA and DI Engineers design closure for test +… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …desire and ability to work in a fast-paced startup environment. + Expert in STA , Synthesis or QOR improvement techniques in the FPGA prototyping or EDA field. The ... annual salary range for California is $150,500 to $279,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …design flow. Experience with design tools such as Incisive/NCSim, Genus/Design Compiler, STA with Tempus/PrimeTime, power analysis. + Experience with Lint and CDC ... tool flows. + Exposure to some major IP and protocols, such as SERDES, PCIe and DDR4. + Self-driven. Good communication, organization, analytical, presentation and people skills. The annual salary range for California is $131,600 to $244,400. You may also be… more
- Broadcom (San Jose, CA)
- …+ Expertise in micro-architecture design and PPA trade-offs. + Experience in synthesis, STA , and timing closure using tools like Synopsys DC or Cadence Genus. + ... Working knowledge of CDC/RDC analysis and debugging using tools such as Spyglass, Questa CDC, or similar. + **Knowledge Areas:** + Solid understanding of digital design fundamentals such as pipelining, FSMs, clock domains, and data paths. + Familiarity with… more