• Senior ASIC Physical

    Capgemini (San Francisco, CA)
    **Job Title : Senior ASIC Physical Design Engineer** **Job Location: Santa Clara, CA (Hybrid)** **Key Responsibilities** + Chip level floor planning, ... US by Capgemini. **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior ASIC Physical Design Engineer_ **Location:** _CA-Santa Clara_… more
    Capgemini (10/16/24)
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  • Senior E/E & Semiconductor Engineer…

    Capgemini (San Francisco, CA)
    ** Physical Design Engineer** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical ... _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design Engineer_ **Location:** _CA-San Francisco_ **Requisition ID:** _077101_ more
    Capgemini (10/16/24)
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  • Sr. SOC/ ASIC Physical Design

    SpaceX (Sunnyvale, CA)
    Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out ... ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON...and weekends as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer/ Senior : $170,000.00 -… more
    SpaceX (11/15/24)
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  • Senior E/E & Semiconductor Engineer…

    Capgemini (San Francisco, CA)
    **Job Role:** ** Physical Design (Synthesis) Engineer** **Job Location : San Jose CA** **Job Description** + At least 7 years of experience in ASIC /SOC ... _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - Physical Design (Synthesis) Engineer_ **Location:** _CA-San Francisco_ **Requisition ID:**… more
    Capgemini (11/12/24)
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  • Senior Physical Design

    Broadcom (San Jose, CA)
    …and features as well as manage extremely large volumes of internet traffic. As a Senior Physical Design Engineer, the ideal candidate will be responsible for ... some of the most complex and cutting edge networking ASIC 's and multi-chip solutions to market over the last...power EM checks. . Methodology & Flow development of Physical Design and Timing Closure. . Interfacing… more
    Broadcom (11/27/24)
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  • COPD (Customer Owned Physical Design

    Broadcom (San Jose, CA)
    …that keep the globe connected. Our ASIC products division is looking for senior , physical design engineering veterans to guide teams designing some of ... Sign-In before you apply.** **Job Description:** Technical Lead for Physical Designs Are you a versatile, senior ...Well verse in EDA tools for physical design verification and sign-off. 6. Knowledge of ASIC more
    Broadcom (11/28/24)
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  • Physical Design Engineer, Annapurna…

    Amazon (Cupertino, CA)
    …handling massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Engineer to help us trail-blaze new ... building an environment that celebrates knowledge-sharing and mentorship. Our senior members enjoy one-on-one mentoring and thorough, but kind,...3yrs in EE/CS - 4+ years of experience in ASIC Physical Design from -… more
    Amazon (11/01/24)
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  • Senior Digital Design Engineer

    Teledyne (Mountain View, CA)
    …of integrated circuits and related development. Participates in all phases of physical design , including floor planning, clock synthesis, timing optimization, ... + Schematic capture + Circuit simulation + Layout and physical design + Debug and verification for...service issues + Advanced level experience with digital and ASIC design + Advanced level experience with… more
    Teledyne (01/08/25)
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  • Sr. Physical Design Methodology…

    Amazon (Cupertino, CA)
    …handling massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze ... Proficient in programming/scripting languages (Perl, Python, C++) - Solid understanding of ASIC physical design , and methodologies including synthesis, place… more
    Amazon (10/18/24)
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  • Senior SoC Technical Program Manager,…

    Amazon (Sunnyvale, CA)
    …phases of Silicon development which are architecture definition, RTL design , Verification, IP design , Physical design , post silicon design and bring ... will interface with cross-functional engineering and program/product management teams to develop ASIC /SOC solutions that will go into Amazon Devices. In this role… more
    Amazon (01/10/25)
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  • Sr. DDR IP Design Engineer (Silicon…

    SpaceX (Sunnyvale, CA)
    …as necessary to support critical milestones COMPENSATION & BENEFITS: Pay range: ASIC /FPGA Design Engineer/ Senior : $170,000.00 - $230,000.00/per year Your ... will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design , validation, product engineering, ASIC implementation). In this… more
    SpaceX (10/21/24)
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  • Sr. Design Verification Engineer (Silicon…

    SpaceX (Sunnyvale, CA)
    …will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design , validation, product engineering, ASIC implementation). In this ... with changing needs and requirements COMPENSATION & BENEFITS: Pay range: Design Verification Engineer / Senior : $170,000.00 - $230,000.00/per year Your… more
    SpaceX (12/05/24)
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  • Senior E/E & Semicon Engineer - Performance…

    Capgemini (San Jose, CA)
    **Job Role: Senior ** **Performance Modeling Engineer** **Job Location: San Jose CA** **Job description:** We are seeking a highly skilled candidate with a strong ... candidate will have a deep understanding of System-on-Chip (SoC) design and architecture, as well as Expertise in performance...+ Experience with Synopsys or Cadence EDA tools and ASIC /SOC Power Analysis Tools. + Deep understanding of SoC… more
    Capgemini (11/14/24)
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  • Senior Power & Performance Engineer

    Microsoft Corporation (Sunnyvale, CA)
    …performance monitors and post-silicon SOC power and performance tuning. + Familiarity with ASIC power analysis, low power design and power optimization. + ... will manage and optimize the Cloud infrastructure. We are looking for a ** Senior Power and Performance Engineer** to join the team. **Responsibilities** + Work with… more
    Microsoft Corporation (12/31/24)
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  • Senior DFT Engineer

    Cisco (San Jose, CA)
    …focus on Design -for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements ... be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with...and post silicon validation phases with additional exposure to physical design signoff activities. What You'll Do… more
    Cisco (10/17/24)
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  • Senior Power Engineer, Platforms,…

    Google (Sunnyvale, CA)
    This is a specialized role which requires physical interaction with hardware equipment in a simulated data center environment, utilizing Google labs, power, and ... equivalent practical experience. + 4 years of experience working in a power converter design including DC/DC converter design and board bring up and debugging… more
    Google (01/08/25)
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  • Sr Sales Executive Semiconductor Engineering…

    Capgemini (San Francisco, CA)
    …At least 5-8 years of experience in complex semiconductor services sales, particularly in ASIC design services. . Minimum of 5 years in Sales Pursuit Management. ... needs aligned with customer product roadmaps. . Engage with senior management levels to strategize pursuits, develop account maps,...foundries, EDA companies, and IP providers. . Background in ASIC Design or Semiconductor Technology R&D is… more
    Capgemini (12/25/24)
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  • Sr. IC Layout Engineer (Silicon Engineering)

    SpaceX (Sunnyvale, CA)
    …who will work alongside world-class cross-disciplinary teams (systems architecture, ASIC design , firmware, pre-silicon verification, post-silicon validation, ... satellite constellation and is providing fast, reliable internet to 3M+ users worldwide. We design , build, test, and operate all parts of the system - thousands of… more
    SpaceX (12/25/24)
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