- Google (Sunnyvale, CA)
- Senior DFT Static Timing Analysis Engineer, Cloud _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving ... equivalent practical experience. + 5 years of experience in static timing (ie, full chip timing...and associated test methodologies. + Experience in Tessent generated DFT timing constraints, SSN bus networks and… more
- Google (Fremont, CA)
- …Testability ( DFT ) implementation. + Experience with industry-standard EDA tools for synthesis, Static Timing Analysis (STA), and DFT . + Experience with ... Senior Silicon Bringup and Test Lead, Raxium _corporate_fare_...advanced DFT techniques such as hierarchical DFT , compression, and diagnosis. + Proficiency in hardware description… more
- Cisco (San Jose, CA)
- …DC/DCG/FC), Verilog/System Verilog programming. **Preferred Qualifications** + Experience in Static Timing Analysis. + Experience with constraint analyzer ... design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes. + Option to also do… more
- Microsoft Corporation (Mountain View, CA)
- …across front-end areas like RTL & VIP Design, Design Verification, Validation, DFT , Emulation, Design Synthesis, RTL Power Anaysis, PD Handoff and SoC integration. ... so that they can deliver cutting-edge silicon solutions for Microsoft. As a Senior Front-End CAD Engineer, you'll drive the development and adoption of cutting-edge… more