- SpaceX (Sunnyvale, CA)
- Sr . ASIC / SOC Verification Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out ... the ultimate goal of enabling human life on Mars. SR . ASIC / SOC VERIFICATION ...weekends as needed COMPENSATION & BENEFITS: Pay range: Design Verification Engineer / Senior : $170,000.00 - $230,000.00/per year… more
- Two95 International Inc. (Sunnyvale, CA)
- Hi, Title: Lead / Senior Verification engineer Location: San Jose, CA...* 5+ or more years of proven experience on ASIC / SoC / IP Verification . ... * Strong experience in SystemVerilog and UVM verification methodologies * Proficiency in Object Oriented programming, computer architecture and data structures * Strong analytical/problem solving skills and pronounced attention to details * Strong… more
- Amazon (Sunnyvale, CA)
- …looking for a Sr . Technical Program Manager with experience in complex ASIC / SOC development of managing various phases of pre-silicon such as architecture, ... front end design, pre-silicon verification , FPGA prototyping, Emulation, Physical design, BROM, FW, substrate...this role you will: - Collaborate with engineering leaders ( ASIC / SOC leads) to create project execution plans… more
- Amazon (Cupertino, CA)
- …scale and rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ... job responsibilities - integrate multiple subsystems into top level SOC , ensure correct clock/reset/functional/DFT signal routing - As a...signal routing - As a key member of the ASIC design team, you will implement and deliver high… more
- Google (Sunnyvale, CA)
- Senior ASIC Power Engineer, ML Accelerators...+ 5 years of experience in logic design, digital ASIC , or SoC design. + Experience with ... behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on… more
- Amazon (Cupertino, CA)
- …analysis and trade-offs - Experience with modern ASIC /FPGA design and verification tools - Experience with SOC bring-up and post-silicon validation Amazon ... validation of AWS next generation ML Chips, Cards and server integration. As a senior member of our hardware team, you will have the outstanding and meaningful… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …who want to make an impact on the world of technology. We are looking for SoC / ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate ... Requirements; US citizenship preferred. + Prior 5-15 years of professional experience in SoC / ASIC Digital Design with focus on Design for Test (DFT) +… more
- Microsoft Corporation (Mountain View, CA)
- …4+ years of experience delivering successful IP or Application Specific Integrated Circuits ( ASIC )/ SOC designs. + 4+ years expertise in Digital Design including ... help achieve that mission. We are looking for a Senior Design Engineer to work in the dynamic Microsoft...Transfer Level (RTL) design, synthesis/Lint/CDC/FEV and System on Chip ( SOC ) integration on different subsystems. Throughout the program you… more
- Microsoft Corporation (Mountain View, CA)
- …5+ years of experience delivering successful IP or Application Specific Integrated Circuits ( ASIC )/ SOC designs. + 4+ years of experience in Synthesis, Timing ... passionate engineers to help achieve that mission. We are looking for a ** Senior Design Engineer** to work in the dynamic Microsoft Artificial Intelligence System on… more
- Google (Fremont, CA)
- …qualifications:** + 15 years of experience in Application-Specific Integrated Circuit/System on Chip ( ASIC / SoC ) design, with a focus on both digital logic design ... Senior Silicon Bringup and Test Lead, Raxium _corporate_fare_...of experience in analog circuit design, including simulation and verification . + Experience working with relevant Electronic Design Automation… more
- Google (Sunnyvale, CA)
- Senior DFT Static Timing Analysis Engineer, Cloud _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving problems, and ... static timing (ie, full chip timing signoff ownership, constraint authoring and verification , full chip static timing analysis and timing ECO creation, timing… more