- Amazon (Cupertino, CA)
- …US, Europe, Singapore, and Japan, and customers across all industries. Custom SoCs (System on Chip ) live at the heart of AWS Machine Learning servers. As a member of ... and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and… more
- Amazon (Cupertino, CA)
- …US, Europe, Singapore, and Japan, and customers across all industries. Custom SoCs (System on Chip ) live at the heart of AWS Machine Learning servers. As a member of ... integration of emergent technologies. We're looking for an ASIC Physical Design Engineer to help us trail-blaze new technologies...of a total compensation package, in addition to a full range of medical, financial, and/or other benefits. For… more
- Google (Sunnyvale, CA)
- …equivalent practical experience. + 5 years of experience in static timing (ie, full chip timing signoff ownership, constraint authoring and verification, full ... Senior DFT Static Timing Analysis Engineer, Cloud _corporate_fare_...Knowledge of semiconductor device physics and SPICE simulation and full - chip static timing topics. **About the job**… more
- Cisco (San Jose, CA)
- …ASIC experience. + Experience with microarchitecture and RTL implementation. + Experience with block/ full chip SDC development in functional and test modes. + ... ** Sr . ASIC Engineer** The application window is expected...will collaborate with Front-end and Back-end teams to understand chip architecture and guide them in refining design and… more
- Celestica (San Jose, CA)
- …to manufacturing. + Conduct thermal simulations, postprocessing, and analysis ranging from chip to facilities level to verify thermal feasibility, risk, and to ... heat transfer hardware. + Consider the thermal aspects of chip packaging technologies. + Apply best-in-class fluid flow geometry...when possible and liquid cooling when necessary to achieve full performance and reliability at the lowest cost. +… more
- Google (Mountain View, CA)
- Senior CPU Architecture and Performance Architect _corporate_fare_ Google _place_ Mountain View, CA, USA; Austin, TX, USA; +3 more; +2 more **Advanced** Experience ... hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Senior CPU Architecture and Performance Architect, you will be the key… more
- Celestica (San Jose, CA)
- …09 **IC/MGR:** Individual Contributor **Direct/Indirect Indicator:** Indirect **Summary** The Senior Lead Software Engineer designs, develops, and maintains software ... and capable of mentoring a team of engineers. The Senior Lead Engineer, Software will work in cross functional...knowledge of BMC related Hardware such as ARM, BMC chip (AST 2500, AST2600, Pilot 4 etc.), HW-monitor and… more
- Google (Fremont, CA)
- Senior Silicon Bringup and Test Lead, Raxium _corporate_fare_ Google _place_ Fremont, CA, USA **Advanced** Experience owning outcomes and decision making, solving ... qualifications:** + 15 years of experience in Application-Specific Integrated Circuit/System on Chip (ASIC/SoC) design, with a focus on both digital logic design and… more
- Cisco (San Jose, CA)
- …CMOS products. * You will lead efforts for a large block on a complex chip , mentor team members and track deliverables, participate in peer review of complex IC ... solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security,… more
- Google (San Francisco, CA)
- …is a part of everything we do. The Data Center Engineering team takes the physical design of our data centers into the future. Our lab mirrors a research and ... make a huge impact. You generate ideas, communicate recommendations to senior -level executives and drive implementation alongside facilities technicians. With your… more
- Micron Technology, Inc. (San Jose, CA)
- …performance and reliability of non-volatile memory products. **Position Overview** The Senior Member of Technical Staff Design Engineer in Micron's NVEG organization ... and optimization of datapath circuits for NAND flash memory. This senior -level position will support design feasibility studies, evaluate impacts, and explore… more
- Cisco (San Jose, CA)
- …lead in San Jose, CA. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive high-quality DFT ... solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security,… more
- Cisco (San Jose, CA)
- …pioneer next-generation Silicon Photonics technologies. You will also engage directly with senior technical leaders and management across Cisco Fabs and the OSAT ... control) and data analysis skills. + Knowledge and experience in physical failure analysis **Preferred Qualifications** + Experience in Silicon Photonic packaging… more
- Amazon (Cupertino, CA)
- …* RTL Development for ML Accelerators * Hardware Architecture & Modeling * Physical Design & Power Optimization * Custom Circuit Design * Pre/Post Silicon Validation ... on your project, whether it's distributed training systems or chip design. Your mentor helps navigate any unfamiliar territory....AI innovation. What sets us apart? Many of our senior engineers began their careers as interns here, creating… more
- Stanford University (Stanford, CA)
- …and constructing novel imaging platform _ad hoc_ to directly visualize these hidden physical parameters present inside and exerted by the cells. We will use optical ... forces and tensions. The precise magnitude and dynamic coordination of these physical parameters are key to _discern how cells interpret and integrate mechanical… more