- SpaceX (Sunnyvale, CA)
- Sr . SOC / ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is ... the ultimate goal of enabling human life on Mars. SR . SOC / ASIC PHYSICAL ...and weekends as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer/ Senior : $170,000.00 - $230,000.00/per year… more
- Capgemini (San Francisco, CA)
- ** Physical Design Engineer** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip ... top level and/or blocks, with experience across the complete ASIC / SOC design flow including routing, static timing...PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design Engineer_ **Location:** _CA-San Francisco_… more
- Amazon (Sunnyvale, CA)
- …complete the execution of projects in time. Key job responsibilities As a Senior SoC Technical Program Manager, you will interface with cross-functional ... you will interface with cross-functional engineering and program/product management teams to develop ASIC / SOC solutions that will go into Amazon Devices. In this… more
- SpaceX (Sunnyvale, CA)
- …as necessary to support critical milestones COMPENSATION & BENEFITS: Pay range: ASIC /FPGA Design Engineer/ Senior : $170,000.00 - $230,000.00/per year Your actual ... Sr . DDR IP Design Engineer (Silicon Engineering) at...cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing… more
- Microsoft Corporation (Sunnyvale, CA)
- …Chip ( SOC ) architectural power models. + Project and report power constrained SOC performance results to senior management. + Maintain the power modeling ... optimize the Cloud infrastructure. We are looking for a ** Senior Power and Performance Engineer** to join the team....SOC power and performance tuning. + Familiarity with ASIC power analysis, low power design and power optimization.… more
- Capgemini (San Francisco, CA)
- …Location : San Jose CA** **Job Description** + At least 7 years of experience in ASIC / SOC project design and development + Hands on with Cadence tools, DFT flow ... & physical aware flow + Prior experience of synthesizing high...digital and software to support the convergence of the physical and digital worlds. Coupled with the capabilities of… more
- Capgemini (San Jose, CA)
- …programming and experience with SimPy. + Experience with Synopsys or Cadence EDA tools and ASIC / SOC Power Analysis Tools. + Deep understanding of SoC design ... **Job Role: Senior ** **Performance Modeling Engineer** **Job Location: San Jose...ideal candidate will have a deep understanding of System-on-Chip ( SoC ) design and architecture, as well as Expertise in… more