- US Tech Solutions (San Francisco, CA)
- …8 years of experience with verification methodologies and languages such as UVM and SystemVerilog . + Experience developing and maintaining verification ... **Job Description:** + The project relates to the design and verification of a custom...in analog and real number modeling preferred **Skills:** + UVM (Universal Verification Methodology) + FPGA tools… more
- Google (Mountain View, CA)
- …5 years of experience with verification methodologies and languages such as UVM and SystemVerilog . + Experience developing and maintaining verification ... scenarios. + Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology ( UVM ) or verify… more
- Meta (Sunnyvale, CA)
- … verification . 10. 10+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies. 11. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Meta (Sunnyvale, CA)
- …in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 11. Experience with Design verification of ... responsible for the verification closure of a design module or sub-system from test-planning, UVM ...development cycles 9. 15+ years of hands-on experience in SystemVerilog / UVM methodology and/or C/C++ based verification… more
- Meta (Sunnyvale, CA)
- …ASIC development cycles 9. 3+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 10. ... responsible for the verification closure of a design module or sub-system from test-planning, UVM ...to joining Meta. 7. 3+ years hands-on experience in SystemVerilog / UVM methodology or C/C++ based verification… more
- Meta (Sunnyvale, CA)
- …development cycles. 10. 5+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies. 11. ... responsible for the verification closure of a design module or sub-system from test-planning, UVM ...practical experience. 8. 5+ years of hands-on experience in SystemVerilog / UVM methodology and/or C/C++ based verification… more
- Meta (Sunnyvale, CA)
- …UVM methodology. 10. 5+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies. 11. Experience ... 9. 5+ years of hands-on experience in Verilog, SystemVerilog , C/C++ based verification and ...14. Experience in development of UVM based verification environments from scratch. 15. Experience with Design… more
- Meta (Sunnyvale, CA)
- … UVM methodology. 9. 3+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies. 10. Experience ... transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs,...13. Experience in development of UVM based verification environments from scratch. 14. Experience with Design… more
- Google (Mountain View, CA)
- …3 years of experience with verification methodologies and languages such as UVM and SystemVerilog . + Experience developing and maintaining verification ... an emphasis on computer architecture. + Experience in low-power design verification . Be part of a diverse...and enhance constrained random verification environments using SystemVerilog and Universal Verification Methodology ( UVM… more
- Google (Sunnyvale, CA)
- … scenarios. + Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology ( UVM ). + Identify ... development of silicon-based ICs and chips. + Experience with SystemVerilog (eg SystemVerilog Assertions or functional coverage)....a related field. + 6 years of experience in design verification . + Experience in power aware… more
- SpaceX (Sunnyvale, CA)
- Design Verification Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out exploring the ... the ultimate goal of enabling human life on Mars. DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX...plans, develop test harnesses and test sequences + Develop SystemVerilog testbench infrastructure (both UVM and non-… more
- Capgemini (San Francisco, CA)
- **Job Title: ASIC Design Verification Infrastructure Engineer (Modern Python experience is must)** **Job Location: Sunnyvale, CA (Remote work is OK)** **Job ... Description:** **Key Responsibilities:** + .Assist the design verification leads to develop software for...basic data structures and algorithms + .Hands-on experience in SystemVerilog / UVM + .Knowledge of UVM … more
- Google (Mountain View, CA)
- …Mixed Signal) designs and mixed mode verification . + Knowledge of analog design basics and experience writing SystemVerilog models of analog blocks using ... practical experience. + 5 years of experience leading digital verification using SystemVerilog for ASIC designs. +... for ASIC designs. + Experience developing and maintaining design verification (DV) testbenches, test cases, and… more
- Amazon (Sunnyvale, CA)
- … engineer. Create UVM verification simulation solutions. The FPGA verification engineer will work with FPGA design and systems teams to define ... legacy constraints. The FPGA verification engineer will work with design and systems teams to define/develop/implement/test/release UVM test environments in… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …In collaboration with R&D, provide in-depth technical assistance to help support advanced verification flows to secure design wins Champion the customer needs ... or PhD degree in Computer Science/Engineering, Electrical Engineering, or related field Verification skills such as UVM testbench architecture, development and… more
- Meta (Sunnyvale, CA)
- …accelerators. 15. Experience with HLS flow for data path implementation. 16. SystemVerilog OVM/ UVM experience. 17. Experience in SoC integration and ASIC ... **Summary:** As a Digital Design Engineer at Meta Reality Labs, you will...Computer Vision/Image Sensing IP. 2. Contribute to chip-level integration, verification plan development and verification . 3. Define… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …, constrained random testing, etc. + Knowledgeable on design and verification languages and methodologies like SystemVerilog , VHDL, C/C++ UVM , ... Solutions at Cadence focusing on the unique requirements of the design and verification community. + Help develop strategy and technology roadmaps for product… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …verification solution (Cadence or others) + Knowledgeable on design and verification languages and methodologies like SystemVerilog , VHDL, C/C++ UVM , ... market. Our team deploys and defines the world leading verification solutions used by top tier hardware design... verification solutions used by top tier hardware design and consumer electronics companies. We work closely with… more
- Siemens Digital Industries Software (Fremont, CA)
- …of emulation systems (Veloce/Zebu/Palladium) highly desirable. + Experience in Verilog/VHDL, Verilog, SystemVerilog , UVM for system level verification + ... **Req ID:** 412822 Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to… more