• Sr. Physical Design

    Amazon (Cupertino, CA)
    …massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze ... - BS + 10yrs or MS + 7yrs in EE/CS - 5+ years developing physical design methodology or CAD flows in synthesis, PNR, and sign-off areas for advanced… more
    Amazon (10/25/25)
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  • Sr. SOC/ASIC Physical Design

    SpaceX (Sunnyvale, CA)
    Sr. SOC/ASIC Physical Design Methodology /CAD Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where ... with the ultimate goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN METHODOLOGY /CAD ENGINEER (SILICON ENGINEERING) At SpaceX we're… more
    SpaceX (12/11/25)
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  • Physical Design Methodology

    Amazon (Cupertino, CA)
    …of machine learning and AI services for our customers' businesses. We are seeking experienced Physical Design Engineer to build the next generation of our ... today. Key job responsibilities - You will create and support innovative physical design methodology and CAD flows. - Develop cloud infrastructure to… more
    Amazon (12/02/25)
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  • Senior Physical Design

    NVIDIA (Santa Clara, CA)
    …human inventiveness and intelligence. What you will be doing: + Developing innovative physical design methodologies for implementation of GPU, CPU and SOCs, with ... PPA (Power, Performance, Area) and runtime improvement of the physical design flow on advanced technology nodes...with internal and external partners to drive tool and methodology improvements to deliver best-in-class PPA solutions across all… more
    NVIDIA (11/19/25)
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  • Senior Timing Methodology Engineer

    NVIDIA (Santa Clara, CA)
    …amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the world's ... aging, self-heating, thermal impact, IR drop etc. + Collaborate with technology leads, VLSI physical design , and timing engineers to define and deploy the most… more
    NVIDIA (11/20/25)
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  • Signoff Methodology Engineer - New…

    NVIDIA (Santa Clara, CA)
    …to amplify human inventiveness and intelligence. We are seeking an innovative Timing Methodology Engineer to help drive multi-physics sign-off strategies for the ... IR drop etc. + Collaborate with technology leads, VLSI physical design , and timing engineers to define...for sign-off. + Knowledge of extraction, device physics, STA methodology and EDA tools limitations. + Shown understanding of… more
    NVIDIA (11/05/25)
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  • Senior Power Integrity Methodology

    NVIDIA (Santa Clara, CA)
    …on the world. We are now looking for a Senior Power Integrity Methodology Engineer . What you'll be doing: + Developing physical design methodologies for ... or related field. + Minimum 5+ years of experience in IR/EM/Thermal flow methodology development and support. + Strong understanding of all aspects of IR/EM/thermal… more
    NVIDIA (10/15/25)
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  • Senior Implementation Methodology

    NVIDIA (Santa Clara, CA)
    …related fields (or equivalent experience). + 8+ years of experience in logic design implementation and/or physical design implementation + Deep understanding ... relative area, timing, and power trade-offs + Strong understanding of physical design implementation eg: physical synthesis, placement, routing, logic… more
    NVIDIA (12/04/25)
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  • Sr. Full Chip Physical Design

    SpaceX (Sunnyvale, CA)
    Sr. Full Chip Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out ... of enabling human life on Mars. SR. FULL CHIP PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)...integrity, etc.) multi-corner and multimode timing closure, process variations, physical verification methodology and tapeout + Familiar… more
    SpaceX (11/14/25)
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  • ASIC Engineer , Physical

    Meta (Sunnyvale, CA)
    …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure...data-path intensive designs 24. Experience in the 3D-IC technology, methodology , and advanced packaging 25. Experience in validating Power… more
    Meta (11/05/25)
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  • Physical IC Design Engineer

    Broadcom (San Jose, CA)
    …Account, please Sign-In before you apply.** **Job Description:** Broadcom is searching for a Physical IC Design Engineer to join the Data Center Solutions ... position will require in-depth knowledge and expertise in all Physical Design aspects of taking RTL to...Tree Synthesis + Floor-planning and Layout + Flow and Methodology Development + Collaborating with IC Design more
    Broadcom (12/10/25)
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  • Physical Design Engineer

    Broadcom (San Jose, CA)
    …Sign-In before you apply.** **Job Description:** Broadcom is looking for a senior level ASIC physical design engineer . In this highly visible role, you will ... and high speed clock constraints and specification. + Good understanding of physical design verification methodology to debug LVS/DRC issues at the chip… more
    Broadcom (09/26/25)
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  • Senior ASIC Physical Design

    NVIDIA (Santa Clara, CA)
    …timing paths through ECOs including crosstalk and noise analysis. + Expertise in physical design and optimization eg, placement, routing, cell sizing, buffering, ... We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If...experience to improve timing convergence flows working with the methodology teams. What we need to see: + BS… more
    NVIDIA (11/22/25)
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  • ASIC Physical Design and Timing…

    NVIDIA (Santa Clara, CA)
    …work, to amplify human inventiveness and intelligence. What you'll be doing: + Drive Physical Design and timing analysis and closure of NVIDIA's GPUs, CPUs, DPUs ... We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If...+ Experience with Static Timing Analysis (STA) + Experience physical design and optimization eg, synthesis, floorplanning,… more
    NVIDIA (10/17/25)
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  • Senior Engineer , Front End Computer Aided…

    Microsoft Corporation (Mountain View, CA)
    …curious engineers to join our Central Front-End Tools, Flows and Methodology (TFM) group. This team drives state-of-the-art converged solutions, automation, and ... assurance checks across front-end areas like RTL & VIP Design , Design Verification, Validation, DFT, Emulation, ...silicon solutions for Microsoft. As a Senior Front-End CAD Engineer , you'll drive the development and adoption of cutting-edge… more
    Microsoft Corporation (12/03/25)
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  • Senior Circuit Design Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior Circuit Design Engineer ! NVIDIA stands at the intersection of hardware excellence and AI breakthrough, where every line of code ... clocking, and power management solutions. + You'll drive the design and physical implementation of custom digital...layout delivery. + Integrate AI/ML techniques directly into the design process and methodology . + Be a… more
    NVIDIA (10/10/25)
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  • Senior Staff Engineer , Hardware…

    Celestica (San Jose, CA)
    …is the brand behind the brands you love in tech and we design , develop, and manufacture leading-edge Hardware Platform Solutions in Networking, Storage, and Server ... drive to find the way for our customers. Let's engineer the future together. Responsible for architecting, implementing, and...and memory. You will work with HW and FW design , mechanical, power, and validation engineers. You will drive… more
    Celestica (11/05/25)
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  • Senior Analog/mixed-signal IC Design

    Cisco (San Jose, CA)
    …deliverables, participate in peer review of complex IC designs and provide solid design methodology from conception to production. * You will also collaborate ... ultra-long haul telecommunication networks. Meet the Team We are Mixed-signal IC design group that develops high speed ()25Gb/s), and high accuracy, analog designs… more
    Cisco (11/14/25)
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  • DFT IC Design Engineer

    Broadcom (San Jose, CA)
    …ATE, ATPG + Hierarchical DFT Flow and Methodology Development + Collaborating with IC Design RTL Engineers and Physical Design Engineers + Must work in ... you apply.** **Job Description:** Broadcom is searching for a DFT IC Design Engineer to join the Data Center Solutions Group. This position involves working… more
    Broadcom (12/10/25)
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  • Senior Layout Mask Design Engineer

    NVIDIA (Santa Clara, CA)
    …spec + Lead and influence other layout designers to improve team efficiency and align design methodology What we need to see: + Associates degree (or equivalent ... We are looking for you! You'll work on the design and development of our next generation custom SRAM...the NVIDIA products! What you'll be doing: + Perform physical layout for custom embedded SRAM structures in state-of-the-art… more
    NVIDIA (11/20/25)
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