• ASIC Design for Test

    Cisco (San Jose, CA)
    ASIC Implementation Technical Lead in San Jose, CA with a primary focus on Design -for- Test . You will work with Front-end RTL teams, backend physical design ... signoff activities. What You'll Do * Responsible for implementing the Hardware Design -for- Test (DFT) features that support ATE, in-system test , debug and… more
    Cisco (11/01/24)
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  • ASIC Design Verification…

    Cisco (San Jose, CA)
    …Bachelor's Degree in EE, CE, or other related field. * 7+ years of related ASIC design verification experience. * Proficient in ASIC verification using ... * Maintain and enhance existing DV environments. * Develop test plans and tests for qualifying design ...design in emulation. * Oversee and manage the ASIC bring-up process. Who You Are The Core Hardware… more
    Cisco (10/01/24)
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  • ASIC Design Verification…

    Cisco (San Jose, CA)
    …to first customer shipments. What You'll Do * You will participate in the ASIC design verification for Cisco high-end switching products. * Development of ... simulation models, test plans, direct and random tests, code or functional...experience * Experience in System Verilog/UVM. * Experience with ASIC design and verification processes, debugging, methodology,… more
    Cisco (10/28/24)
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  • ASIC Engineer , Design

    Meta (Menlo Park, CA)
    …world-class complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure...integration 6. Collaboration with verification and emulation teams in test plan development and debug 7. Collaboration with implementation… more
    Meta (10/18/24)
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  • ASIC Design Verification…

    Cisco (San Jose, CA)
    …You'll Work With: You will be in the Silicon One development organization as an ASIC design verification engineer in San Jose, CA. You collaborate closely ... for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers...designers, hardware and cross functional teams to verify the ASIC in simulation, in emulation and during ASIC more
    Cisco (11/01/24)
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  • ASIC Engineer , Infra Silicon

    Meta (Menlo Park, CA)
    …entire Silicon Lifecycle to build and scale silicon for data center applications.As an ASIC Engineer in the Silicon Lifecycle Engineering team, you will be part ... The role also involves partnering with Full Stack Software, Hardware, ASIC Design , Verification, Emulation, Pre/Post-Silicon Validation & Systems teams… more
    Meta (10/24/24)
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  • ASIC Engineer , Design

    Meta (Menlo Park, CA)
    …world-class complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration. 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure...and integration. Collaboration with verification and emulation teams in test plan development and debug. 5. Collaboration with implementation… more
    Meta (10/09/24)
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  • ASIC Engineer , Design

    Meta (Menlo Park, CA)
    …world-class complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure...integration 5. Collaboration with verification and emulation teams in test plan development and debug 6. Collaboration with implementation… more
    Meta (10/16/24)
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  • Asic Design Verification…

    Broadcom (San Jose, CA)
    …Controllers/Wireless Charging Chips and other new initiatives. As a verification engineer , your responsibilities will include: ○ Architect block and full-chip ... with embedded CPUs and mixed signal interfaces. ○ Develop test plans and coverage metrics from specifications and write...○ Debug RTL and Gate simulations and work with design engineers to verify fixes. ○ Write diagnostics for… more
    Broadcom (11/01/24)
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  • ASIC Engineer

    Cisco (San Jose, CA)
    …/lead to engage in new development of our UCS family. You will have an ASIC design and verification background with hands-on experience in RTL verification and ... ASIC bring up Minimum Qualifications * 8+ years ASIC design verification experience with Bachelor's or...and top level for SoC * Prior experience building test benches from scratch, hands on experience with System… more
    Cisco (10/01/24)
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  • ASIC Lead Engineer , Project Taara…

    Google (Mountain View, CA)
    ASIC Lead Engineer , Project Taara (Fixed Term) Hardware Engineering Mountain View, CA This is a fixed-term contract position for 12 months About the team: At X ... About the Role: The Taara Project is seeking an ASIC lead engineer to drive the next...design , own the foundry submission process, oversee physical test on returning hardware, and coordinate a small team… more
    Google (10/18/24)
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  • ASIC Implementation Engineer

    Broadcom (San Jose, CA)
    …a Candidate Account, please Sign-In before you apply.** **Job Description:** ASIC implementation engineer with demonstrated expertise in multiple disciplines ... including synthesis, design for test , floorplanning, place and route,...Engineering or Computer Enginering and 8+ years of related ASIC implementation experience. Post graduate degree in EE/CE is… more
    Broadcom (11/01/24)
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  • Design Verification (DV) Engineer

    Cisco (San Jose, CA)
    …being developed in the industry. What You'll Do You will participate in the ASIC design verification and Emulation for Cisco high-end switching products. One of ... and Wireless products. With approximately 2,100 employees across 16 countries, we design the networking hardware for Enterprises and Service Providers of various… more
    Cisco (10/30/24)
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  • Physical Design Engineer

    Cisco (San Jose, CA)
    ASIC Implementation Technical Lead in San Jose, CA with a primary focus on Design -for- Test . You will work with Front-end RTL teams, backend physical design ... activities. What You'll Do You will be part of ASIC physical design Team which is responsible...physical implementation from RTL to GDSII. As Physical Verification Engineer your main responsibilities will include: * Perform full… more
    Cisco (10/23/24)
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  • Senior Digital Design Engineer

    Teledyne (Mountain View, CA)
    …for current and emerging challenges. Teledyne Microwave Solutions is hiring a Digital Design Engineer that will be responsible for the digital design ... test strategies, devices, and systems + Utilize CMOS design tools such as Cadence, Mentor, Synopsis, Libero and...service issues + Advanced level experience with digital and ASIC design + Advanced level experience with… more
    Teledyne (10/10/24)
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  • Senior Design Engineer

    Micron Technology, Inc. (San Jose, CA)
    …over the world and support the efforts of groups such as Product Engineering, Test , Probe and Process Integration to proactively design products that optimize ... and assure the best cost, quality, reliability, time-to-market, and customer satisfaction. As an Engineer - NVE Design at Micron Technology, Inc., you will be a… more
    Micron Technology, Inc. (10/17/24)
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  • IC Design Engineer

    Broadcom (San Jose, CA)
    …STA, RTL/gate level simulations & silicon debug + Scripting for various IC design tasks such as STA, equivalency checks, test bench, simulations, synthesis, ... + prepare block level resource requirements & development schedule + generate verification & test plans for design validation + Perform design tradeoff… more
    Broadcom (11/01/24)
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  • Sr. Digital Design Engineer

    Integense (San Jose, CA)
    …+ Develop design automation tools/scripts as appropriate. + Work with Test Engineering to ensure that the end-product is testable and robust. Minimum ... Integense Micro is disrupting the semiconductor supply chain with innovative ASIC solutions. As an established provider of integrated circuit solutions for the… more
    Integense (09/25/24)
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  • Physical Design Methodology Engineer

    quadric.io, Inc (Burlingame, CA)
    …What We Expect: Initiative, Collaboration, Completion Role As a member of our physical design methodology team you will be tasked with developing physical design ... scripts from RTL to GDS across multiple advanced process nodes. + Preform test chip tape outs as necessitated by architecture innovation. + Collaborate with the… more
    quadric.io, Inc (10/05/24)
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  • Signal Integrity Engineer , (Nextest, San…

    Teradyne (San Jose, CA)
    …measurements + Able to develop test fixtures for making measurements (both custom design test boards as well as making "ad hoc" probing solutions to ... Teradyne is looking for a highly-motivated, energetic, technically driven engineer to focus on the development of hardware for...simulation tools as well as the development of physical test fixtures to verify design . They will… more
    Teradyne (10/23/24)
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