- Broadcom (San Jose, CA)
- …in Electrical Engineering or Computer Engineering with 10+ years of experience in Physical design or PhD in Electrical Engineering or Computer Engineering with ... 7+ years of experience in Physical design . + Deep knowledge about industry...TSMC 7nm-2nm, ie understanding of power consumptions, area, estimated design and layout efforts for digital blocks,… more
- Capgemini (San Francisco, CA)
- ** Physical Design Engineer** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical ... candidate should have a high aptitude for floor-planning the design of complex digital top level and/or...PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design Engineer_ **Location:**… more
- Cisco (San Jose, CA)
- … ASIC team can provide. You will work with exceptional talent with vast ASIC design and development expertise. With Cisco being a systems company, you will ... refining design and timing constraints for seamless physical design closure. As part of this...with STA tools like PrimeTime/Tempus * Understanding of related digital design concepts (eg. clocking and async… more
- Cisco (San Jose, CA)
- …team to address design bugs and close code coverage. * Work closely with physical design team to close design timing and place-and-route issues. * ... With You will work with exceptional talent with vast ASIC design and development expertise. With Cisco...to develop innovative technology and power a more inclusive, digital future for everyone. How do we do it?… more
- Capgemini (San Francisco, CA)
- **Job Title : Senior ASIC Physical Design Engineer**... and software to support the convergence of the physical and digital worlds. Coupled with the ... US by Capgemini. **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior ASIC Physical Design Engineer_ **Location:** _CA-Santa Clara_… more
- Cisco (San Jose, CA)
- …You will work with outstanding talent and vast ASIC development expertise in design , DV, DFT, physical design , and post-silicon validation The team ... What You'll Do * You will participate in the ASIC design verification for Cisco high-end switching...develop innovative technology, and to power a more inclusive, digital future for everyone. How do we do it?… more
- Capgemini (San Francisco, CA)
- **Job Title: ASIC Design Verification Infrastructure Engineer (Modern Python experience is must)** **Job Location: Sunnyvale, CA (Remote work is OK)** **Job ... Description:** **Key Responsibilities:** + .Assist the design verification leads to develop software for internal solutions/generators... and software to support the convergence of the physical and digital worlds. Coupled with the… more
- Cisco (San Jose, CA)
- …focus on Design -for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements ... be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with...and post silicon validation phases with additional exposure to physical design signoff activities. What You'll Do… more
- Cisco (San Jose, CA)
- …basis to address design bugs and close code coverage. * Work closely with physical design team to close design timing and place-and-route issues * ... Do Be part of the development organization as an ASIC Engineering Technical Leader with primary focus on RTL... Engineering Technical Leader with primary focus on RTL Design . * Create micro-architecture specifications and participate in reviews… more
- Cisco (San Jose, CA)
- …processor architecture, Ethernet processing, digital signal processing, high-speed logic design & verification, memory designs, and physical design ... and efficient memory designs, custom library development (Standard Cell and I/O), physical design & DFT, Signal Integrity, and complexed packaging technology.… more
- Cisco (San Jose, CA)
- …focus on Design -for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements ... be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with...and post silicon validation phases with additional exposure to physical design signoff activities. What You'll Do… more
- Cisco (San Jose, CA)
- …strategies, and correlation between PNR, Spice, and STA, along with advising the Physical Design team on best practices. * Additionally, you'll develop ... accuracy. Who you'll work with You will collaborate with ASIC Front-end and Back-end teams to understand chip architecture...refining design and timing constraints for seamless physical design closure. As part of this… more
- Google (Mountain View, CA)
- …or Clocks/Reset. + Knowledge of ASIC Verification, DFT, synthesis, STA, or Physical Design . + Knowledge of high performance and low-power design ... with an emphasis on computer architecture. + Experience with ASIC design methodologies for clock domain checks,...+ Work closely with the multi-site cross-functional teams: Verification, Design for Test, Physical Design … more
- Broadcom (San Jose, CA)
- … design trade-offs. You will collaborate closely with verification engineers and physical design teams to ensure functional correctness, timing closure, and ... and Timing Closure:** + Perform synthesis and work with physical design teams to achieve timing closure...or similar. + **Knowledge Areas:** + Solid understanding of digital design fundamentals such as pipelining, FSMs,… more
- Teledyne (Mountain View, CA)
- …analyzing, and summarizing development and service issues + Advanced level experience with digital and ASIC design + Advanced level experience with ... capabilities for current and emerging challenges. Teledyne Microwave Solutions is hiring a Digital Design Engineer that will be responsible for the digital… more
- Google (Mountain View, CA)
- …5 years of experience leading digital verification using SystemVerilog for ASIC designs. + Experience developing and maintaining design verification (DV) ... . + Plan and execute on the verification of digital and mixed signal design blocks by...+ Work closely with system, software, design , Design for testing (DFT) and physical implementation… more
- Cisco (San Jose, CA)
- …as per need for verification robustness. * Guide and mentor a team of physical design engineers on project-level backend implementation and partner closely with ... Science, with 10+ year minimum of hands-on experience in ASIC implementation and Physical verification * Experience...Experience working with one or more of the following physical design tools, such as Cadence, Innovus,… more
- Capgemini (San Francisco, CA)
- **Job Role:** ** Physical Design (Synthesis) Engineer** **Job Location : San Jose CA** **Job Description** + At least 7 years of experience in ASIC /SOC ... and software to support the convergence of the physical and digital worlds. Coupled with the...PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - Physical Design (Synthesis) Engineer_ **Location:** _CA-San Francisco_… more
- quadric.io, Inc (Burlingame, CA)
- …Happiness What We Expect: Initiative, Collaboration, Completion Role As a member of our physical design methodology team you will be tasked with developing ... physical design methodologies and automation scripts for...technologies. Nice to haves: + Knowledge of lower power digital design techniques. + IP integration experience.… more
- Capgemini (San Francisco, CA)
- …SoC integration as needed **Requirements:** . Minimum 10 years of strong experience in Digital design at RTL level using Verilog / SystemVerilog . Experience ... will consider remote.** **Job description:** . As an RTL Design Engineer you will be responsible for ASIC... and software to support the convergence of the physical and digital worlds. Coupled with the… more