• ASIC Digital Physical

    Broadcom (San Jose, CA)
    …PhD in Electrical Engineering or Computer Engineering with 10+ years of experience in Physical design . + Deep knowledge about industry standards in Physical ... Power-grid and high speed clock constraints and specification. + Good understanding of physical design verification methodology to debug LVS/DRC issues at the… more
    Broadcom (11/01/24)
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  • Senior E/E & Semiconductor Engineer - ASIC

    Capgemini (San Francisco, CA)
    ** Physical Design Engineer** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical ... candidate should have a high aptitude for floor-planning the design of complex digital top level and/or...PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design Engineer_ **Location:**… more
    Capgemini (10/16/24)
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  • ASIC Design Verification Engineer

    Cisco (San Jose, CA)
    …You will work with outstanding talent and vast ASIC development expertise in design , DV, DFT, physical design , and post-silicon validation The team ... What You'll Do * You will participate in the ASIC design verification for Cisco high-end switching...develop innovative technology, and to power a more inclusive, digital future for everyone. How do we do it?… more
    Cisco (10/28/24)
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  • Senior ASIC Physical Design

    Capgemini (San Francisco, CA)
    **Job Title : Senior ASIC Physical Design Engineer**... and software to support the convergence of the physical and digital worlds. Coupled with the ... US by Capgemini. **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior ASIC Physical Design Engineer_ **Location:** _CA-Santa Clara_… more
    Capgemini (10/16/24)
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  • ASIC Design for Test Technical…

    Cisco (San Jose, CA)
    …focus on Design -for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements ... be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with...and post silicon validation phases with additional exposure to physical design signoff activities. What You'll Do… more
    Cisco (08/16/24)
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  • ASIC Engineer II (Intern) United States

    Cisco (San Jose, CA)
    …and efficient memory designs, custom library development (Standard Cell and I/O), physical design & DFT, Signal Integrity, and complexed packaging technology. ... the latest deep submicron silicon process nodes with ownership extending to complete in-house physical design . Who You Are * Ability to manage multiple tasks and… more
    Cisco (09/14/24)
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  • ASIC Lead Engineer, Project Taara (Fixed…

    Google (Mountain View, CA)
    design will include analog mixed signal, radio frequency focused, and digital design for free-space optical communication links including; analog front-end, ... ASIC Lead Engineer, Project Taara (Fixed Term) Hardware...input from various teams, contribute to the detailed circuit design , own the foundry submission process, oversee physical more
    Google (10/18/24)
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  • ASIC Engineering Technical Leader

    Cisco (San Jose, CA)
    …basis to address design bugs and close code coverage. * Work closely with physical design team to close design timing and place-and-route issues * ... Do Be part of the development organization as an ASIC Engineering Technical Leader with primary focus on RTL... Engineering Technical Leader with primary focus on RTL Design . * Create micro-architecture specifications and participate in reviews… more
    Cisco (11/01/24)
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  • ASIC Engineer II (Full Time) United States

    Cisco (San Jose, CA)
    …processor architecture, Ethernet processing, digital signal processing, high-speed logic design & verification, memory designs, and physical design ... and efficient memory designs, custom library development (Standard Cell and I/O), physical design & DFT, Signal Integrity, and complexed packaging technology.… more
    Cisco (10/25/24)
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  • ASIC Design Engineer, Core IP

    Google (Mountain View, CA)
    …ensure functionality of the design . + Provide input on synthesis, timing closure, and Physical Design of digital blocks. + Take a leadership role on ... field, or equivalent practical experience. + 5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog… more
    Google (10/31/24)
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  • ASIC Engineering Technical Leader

    Cisco (San Jose, CA)
    …focus on Design -for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements ... be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with...and post silicon validation phases with additional exposure to physical design signoff activities. What You'll Do… more
    Cisco (10/19/24)
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  • Hardware Engineering Intern, PhD, Summer

    Google (Mountain View, CA)
    …Computer Architecture, Digital Design Verification, Digital Circuits, ASIC Physical Design , FPGAs, Embedded Systems, Memory Systems. Preferred ... + Experience with board layout (eg, working with CAD/PCB design ), Systems Integration, RF, Hardware Test, or Antenna. As...core Consumer Hardware products. The teams you work with design , develop, and deploy next generation consumer hardware while… more
    Google (10/08/24)
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  • Physical Design Engineer

    Cisco (San Jose, CA)
    …testing some of the most complex ASICs being developed. Your Impact As a physical design engineer you will be spearheading the implementation of complex ... multi-hierarchy designs, ensuring robust physical design processes like logic synthesis and...design of an end-to-end IP or integration of ASIC /SoC design . * Design custom… more
    Cisco (11/05/24)
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  • Senior Digital Design Engineer

    Teledyne (Mountain View, CA)
    …analyzing, and summarizing development and service issues + Advanced level experience with digital and ASIC design + Advanced level experience with ... capabilities for current and emerging challenges. Teledyne Microwave Solutions is hiring a Digital Design Engineer that will be responsible for the digital more
    Teledyne (10/10/24)
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  • Physical Design Methodology Engineer

    quadric.io, Inc (Burlingame, CA)
    …Happiness What We Expect: Initiative, Collaboration, Completion Role As a member of our physical design methodology team you will be tasked with developing ... physical design methodologies and automation scripts for...technologies. Nice to haves: + Knowledge of lower power digital design techniques. + IP integration experience.… more
    quadric.io, Inc (10/05/24)
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  • RTL Design Engineer

    Capgemini (San Francisco, CA)
    …SoC integration as needed **Requirements:** . Minimum 10 years of strong experience in Digital design at RTL level using Verilog / SystemVerilog . Experience ... will consider remote.** **Job description:** . As an RTL Design Engineer you will be responsible for ASIC... and software to support the convergence of the physical and digital worlds. Coupled with the… more
    Capgemini (10/12/24)
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  • IC Design Engineer

    Broadcom (San Jose, CA)
    …experience_ + Good knowledge of ARM subsystem + Good knowledge of high speed digital circuit design . + Good knowledge of digital upsampling/downsampling + ... This opening is for working on chips that enable Physical Layer Products for High Speed Optical Communication. +...network. + Good knowledge on FEC (Forward Error Correction) design . + Good knowledge of digital signal… more
    Broadcom (11/01/24)
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  • Signal Integrity Technical Lead

    Cisco (San Jose, CA)
    …and standards. Your work will include electromagnetic modeling, gigabit serial link design , power delivery network analysis, and physical measurements for ... years of related experience * Experience working directly with ASIC , package, and system design teams to...and analyzing power delivery networks. * Experience in conducting physical measurements to collect data for design more
    Cisco (08/08/24)
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  • R&D Engineer

    Broadcom (San Jose, CA)
    …industry for IP and chip design + Working knowledge of IP and chip design flow for analog and digital + Experience with parametric and yield data analysis. ... extraction and simulation, abstract and LEF/DEF generation, LVS/ERC checks, physical verification + Conducting design reviews &...from manufacturing, technology and packaging **Job Description** + Provide design support for IP & ASIC to… more
    Broadcom (11/01/24)
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  • Signal Integrity Engineer, (Nextest, San Jose, CA)

    Teradyne (San Jose, CA)
    …require good working knowledge of common simulation tools as well as the development of physical test fixtures to verify design . They will also be expected to ... problems across all memory products at Teradyne. This includes ASIC to board signaling, ASIC to ...help with design review of critical PCBs for signal integrity concerns.… more
    Teradyne (10/23/24)
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