- Cisco (San Jose, CA)
- …noise, while managing ECO tasks. * Your role may include extraction and STA flow development, convergence strategies, and correlation between PNR, Spice, and STA ... practices. * Additionally, you'll develop methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive execution to… more
- Capgemini (San Francisco, CA)
- **Physical Design Engineer ** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip ... _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design Engineer_ **Location:** _CA-San Francisco_… more
- Capgemini (San Francisco, CA)
- **Job Title : Senior ASIC Physical Design Engineer ** **Job Location: Santa Clara, CA (Hybrid)** **Key Responsibilities** + Chip level floor planning, ... integration and ECO generation. + Expertise in timing closure ( STA ) of high frequency blocks + Handling blocks of...towards Intelligent Industry. Capgemini Engineering has more than 55,000 engineer and scientist team members in over 30 countries… more
- Broadcom (San Jose, CA)
- …please Sign-In before you apply.** **Job Description:** **Job Description:** + ASIC implementation engineer with demonstrated expertise in multiple disciplines ... place and route, clock methodology, power planning and analysis, timing closure, STA , signal integrity and physical design checks. + Participate in large complex… more
- Cisco (San Jose, CA)
- …as a team. Your Impact You are a detail-oriented Timing Constraint (SDC) Engineer with strong analytical skills and a deep understanding of timing constraints, ... including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/ STA tools and scripting for automation, you excel at identifying and… more
- Cisco (San Jose, CA)
- …ASICs being developed. Your Impact You are a detail-oriented Test Timing Engineer with strong analytical skills and a deep understanding of timing constraints, ... validation, CDC delay check, and SDC flow development. * STA runs, more specifically at scan modes along with...including standard cells/memory/IO/IP modeling and its usage in the ASIC flow. * Background in debugging and analyzing timing… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …to make an impact on the world of technology. The position is part of Palladium ASIC development team . The team is responsible for all the ASICs that go into the ... of the usage modes and debug tools. The Palladium ASIC team has a wide range of expertise from...Experience with design tools such as Incisive/NCSim, Genus/Design Compiler, STA with Tempus/PrimeTime, power analysis. + Experience with Lint… more
- Broadcom (San Jose, CA)
- …desired PPA metrics. Candidate would also be required to do equivalence checks, STA , Timing closure and power optimization. Should be able to implement timing and ... expertise in place and route and/ or timing (constraints, STA ) can be considered for this position. Candidate should...with timing analysis and place and route tools for ASIC / SoC Design is a must. Should have worked… more
- Renesas (San Jose, CA)
- Senior Staff Engineer , Electrical Design Job Description + Propose, Architect, and Design RTL in Verilog for use in a Mixed Signal Integrated Circuit + Contribute ... route netlists + Fluent in Verilog RTL coding and ASIC design methodology is a must + Competence in...must + Competence in developing design constraints for synthesis, STA and P&R hand-off + Experience with gate-level simulations,… more
- Broadcom (San Jose, CA)
- …timing constraint file + RTL coding, Lint checks, CDC, Synthesis, Equivalency checking, STA , RTL/gate level simulations & silicon debug + Scripting for various IC ... design tasks such as STA , equivalency checks, test bench, simulations, synthesis, etc. +...manufacturing. + Good Knowledge in languages relevant to the ASIC development process including Verilog, VHDL, Unix/Perl Scripting or… more
- Capgemini (San Francisco, CA)
- **Job Role:** **Physical Design (Synthesis) Engineer ** **Job Location : San Jose CA** **Job Description** + At least 7 years of experience in ASIC /SOC project ... + Conformal LEC (Priority #1) + Synthesis tools (Synposys & Cadence) + Timing/ STA tools (PrimetimeSI & Cadence tools). **Life at Capgemini** Capgemini supports all… more
- Broadcom (San Jose, CA)
- …Account, please Sign-In before you apply.** **Job Description:** Broadcom's ASIC Product Division is seeking candidates for HBM/DDR/SERDES Verification Lead ... Engineer position at our San Jose, California Development Center....drive innovation within the team. + Working closely with STA and DI Engineers design closure for test +… more
- Cisco (San Jose, CA)
- …Work With You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with a primary focus on Design-for-Test. ... off checklist and reviews for chip tape out, including test coverage, STA . * Prior experience pre-silicon DFT implementation and verification flows, and post-silicon… more