- Cisco (San Jose, CA)
- …some of the most complex ASICs being developed in the industry. Your Impact As an ASIC Engineering Technical Leader, you will be responsible for leading the ... Degree in Electrical or Computer Engineering with 10 Years Experience with ASIC design timing closure flow ( STA ) and methodology. * Hands-on experience with… more
- Cisco (San Jose, CA)
- …and related documentation. Minimum Qualifications: * Bachelor's Degree in Electrical or Computer Engineering with 12+ years of ASIC or related experience or ... clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/ STA tools and scripting for automation, you excel at...Master's Degree in Electrical or Computer Engineering with 8+ years of ASIC or… more
- Broadcom (San Jose, CA)
- …a Candidate Account, please Sign-In before you apply.** **Job Description:** **Senior Custom ASIC Engineering Lead** Are you a versatile, senior engineer capable ... internal cross-functional teams in areas such as physical design, STA , DFT, and packaging? Have you taped out so...note about avoiding them in future? Do you love technical -deep-dive with engineers and providing an eagle's eye summary… more
- Meta (Menlo Park, CA)
- …with focus on the impact they can create as part of a world-class engineering team. **Required Skills:** ASIC Package Engineer SI/PI Responsibilities: 1. Drive ... Minimum Qualifications: 10. Bachelor's degree in Computer Science, Computer Engineering , relevant technical field, or equivalent practical experience.… more
- Cisco (San Jose, CA)
- …(Experience with both H-Tree and Clock Mesh architectures). * Interface with Fullchip STA team on timing constraints. * Power Planning and Robust Power Grid planning ... * Fullchip Physical Verification. Minimum Qualifications * Bachelor's degree in Electrical Engineering or equivalent similar experience. * 10+ years of experience in… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …to make an impact on the world of technology. The position is part of Palladium ASIC development team . The team is responsible for all the ASICs that go into the ... of the usage modes and debug tools. The Palladium ASIC team has a wide range of expertise from...Job Requirements: + Bachelor's in Computer Science or Electrical Engineering + 2 years of related experience; or Master's… more
- Google (Mountain View, CA)
- …for clock domain checks, reset checks and low power design. + Knowledge of ASIC Verification, DFT, synthesis, STA , or Physical Design. + Knowledge of high ... Minimum qualifications: + Bachelor's degree in Electrical Engineering , Computer Engineering , Computer Science, or...and development, and provide feedback and coaching. + Provide technical leadership to engineers and model design practices (ie… more
- Broadcom (San Jose, CA)
- …Candidate Account, please Sign-In before you apply.** **Job Description:** Broadcom ASIC product division is a leader in semiconductor innovation, delivering ... critical handling of clock and reset domains crossings. **Key Responsibilities:** ** Technical Leadership and Domain Expertise:** + Lead the design and implementation… more
- Broadcom (San Jose, CA)
- …ASICs (Multi-100 million gates complexity). + Demonstrated ability in providing technical support to customers and managing customer working relationships + ... Demonstrated strong technical hands-on competency in using leading edge physical design...challenges of designing in deep sub-micron processes and state-of-the-art ASIC design for AI/ computing and networking products **Qualifications… more