- Capgemini (San Francisco, CA)
- … Engineer ** **Job Location:** **San Francisco CA** **Job Description** We are seeking Digital Design / RTL Design engineer for our Full Time Employment ... 5 to 10 years of strong experience in Digital design at RTL level using Verilog/System Verilog...towards Intelligent Industry. Capgemini Engineering has more than 55,000 engineer and scientist team members in over 30 countries… more
- Capgemini (San Jose, CA)
- …**Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - Logic Design ( RTL ) Engineer_ **Location:** _CA-San ... **Job Role : Senior RTL Engineer ** **Job Location : San...related field. + 10 years of experience in Logic ( RTL ) Design , SystemVerilog, Verilog/VHDL, Spyglass tool, Synopsys/Cadence… more
- Google (Mountain View, CA)
- …field, or equivalent practical experience. + 5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog ... integration. In this role, you will be responsible for Register-Transfer Level ( RTL ) design development of camera and machine learning designs. This includes … more
- Google (Mountain View, CA)
- …field, or equivalent practical experience. + 5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog ... SystemVerilog. + Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power... code, performance and power as well as low-power design techniques. Preferred qualifications: + Master's degree or PhD… more
- Google (Mountain View, CA)
- …Engineering, Computer Science or equivalent practical experience. + Experience with digital logic design principles, RTL design concepts, and use of Verilog ... + Contribute to CPU frontend designs, emphasizing on microarchitecture and RTL design for the next generation CPU. + Propose performance enhancing… more
- Google (Mountain View, CA)
- …field, or equivalent practical experience. + 10 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog ... CPU subsystem. Develop CPU subsystem front-end designs, emphasizing on microarchitecture and RTL design for the next generation CPU. + Communicate the pros and… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …but is not limited to: + Digital microarchitecture definition and documentation + RTL logic design , debug and functional verification + Strong background in ... and developing flows at all phases of the digital design and functional verification. It is further expected that...well as a thorough understanding of the end-to-end digital design flow in order to accurately and efficiently collaborate… more
- Broadcom (San Jose, CA)
- …applications. We are seeking a staff **Digital Front-End Designer** with deep expertise in RTL design , synthesis, and design optimization to drive the ... micro-architecture, and PPA trade-offs to optimize performance, power, and area. ** RTL Design and Micro-Architecture:** + Develop high-quality RTL designs… more
- Google (Mountain View, CA)
- …field, or equivalent practical experience. + 5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog ... on computer architecture. + 10 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.… more
- Google (Mountain View, CA)
- …accelerate chip design . + Solve some of the most complex tasks in Chip Design ( RTL generation, RTL verification, Logic Synthesis, Physical Design , ... Key responsibilities: + Contribute and drive ML for Physical Design , Logical Synthesis, Verification and RTL generation....to set you up for success as a Research Engineer at Google DeepMind, we look for the following… more
- Cisco (San Jose, CA)
- …contribute to chip architecture definition and discussions. * Author design specifications and participate in micro-architecture specification reviews. * Implement ... Verilog RTL to meet timing and performance requirements. * Help...performance requirements. * Help define, evolve, and support our design methodology. * Mentor junior engineers on performing project… more
- Cisco (San Jose, CA)
- …close fullchip timing in multiple timing modes. * Option to also do block level RTL design or block or top-level IP integration. * Helping develop efficient ... first customer shipments. Your Impact You are a diligent Design /SDC Engineer with strong analytical skills and...block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development. *… more
- Belcan (Palo Alto, CA)
- Sr. Physical Design Engineer Job Number: 354330 Category: Design Engineering Description: Job Title: Sr. Physical Design Engineer Pay rate: $66.34 ... Keywords: #PaloAltoJobs; #PhysicalDesignEngineerjobs; Job Description: As a Sr. physical design engineer , you will contribute to all...address timing, congestion and power issues. In-Depth Knowledge of design flow from RTL to GDSII. Good… more
- Google (Mountain View, CA)
- …field, or equivalent practical experience. + 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog ... SystemVerilog. + Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power... code, performance and power as well as low-power design techniques. Preferred qualifications: + Master's degree or PhD… more
- Cisco (San Jose, CA)
- …an ASIC Implementation Technical Lead in San Jose, CA with a primary focus on Design -for-Test. You will work with Front-end RTL teams, backend physical design ... design Team which is responsible for full Chip physical implementation from RTL to GDSII. As Physical Verification Engineer your main responsibilities will… more
- Broadcom (San Jose, CA)
- …Account, please Sign-In before you apply.** **Job Description:** **Job Description: IC Design Engineer ** + Participate in IP level architectural definition ... including micro-architecture definition + Perform RTL design using Verilog HDL, with an emphasis on performance and area + Implement multi-power and low-power… more
- Cisco (San Jose, CA)
- …coverage through implementation and review of code and functional coverage. * Ensure RTL quality with qualifying the design with Gate Level Simulations on ... for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers,...is on the lookout for a driven Senior Verification Engineer to join us in developing the next generation… more
- Meta (Menlo Park, CA)
- …SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration. 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to build...development. 3. RTL development using Verilog, System Verilog and HLS. 4.… more
- Cisco (San Jose, CA)
- …and participate in specification and test plan reviews. * Architect and implement complex RTL designs. * Implement Verilog RTL to meet timing and performance ... coverage closure. * Collaborate with the verification and physical design teams to resolve block level issues. * Perform...Electrical or Computer engineering and 5+ years of ASIC Design experience or Master's degree in Electrical or Computer… more
- Capgemini (San Jose, CA)
- …_Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - Mixed-Signal Design Verification Engineer_ **Location:** _CA-San ... **Job Role: Senior** **Mixed Signal DV Engineer ** **Job Location: San Jose CA** **Job description:**...This role will provide the ability to directly influence design related changes as required to meet functional specifications.… more