- Cadence Design Systems, Inc. (San Jose, CA)
- …is not limited to: + Digital microarchitecture definition and documentation + RTL logic design , debug and functional verification + IP integration and ... front-end coding, scripting and developing flows at all phases of the digital design and functional verification. It is further expected that the candidate will… more
- Microsoft Corporation (Mountain View, CA)
- …Integrated Circuits (ASIC)/SOC designs and expertise in Digital Design including microarchitecture specification development, RTL coding in Verilog/System ... clients, and augmented reality. We are looking for a ** Principal Design Engineer** to work in the...on Intellectual Property (IP) microarchitecture specification, Register Transfer Level ( RTL ) design , synthesis, and System on Chip… more
- Micron Technology, Inc. (San Jose, CA)
- …build design architecture spec documents for the new features * Assist in design and development of schematics and/or RTL blocks _Lead and Develop Projects ... be responsible for leading and mentoring highly technical teams, crafting, and analyzing digital circuits used in the development of memory products. **This role is… more
- Qualcomm (San Jose, CA)
- …to help create a smarter, connected future for all. As a Qualcomm Digital ASIC Engineer, you will define, model, design , optimize, verify, validate, ... route, timing and power use, and verification or similarly for custom circuit design /layout flow. * Utilizes tools/applications (eg, RTL to GDS Flow, Virtuoso)… more
- Microsoft Corporation (Mountain View, CA)
- …Memory Physical Layer **(** DRAM PHY) and Interface Protocol(DFI) and High speed digital design experience. **Other Requirements:** + Ability to meet Microsoft, ... and partners worldwide and we are looking for a ** Principal Logic Engineer** to help achieve that mission. As...blocks of a DRAM Memory Controller and implement the design with high quality in Verilog Register Transfer Level… more
- Microsoft Corporation (Mountain View, CA)
- …inclusion where everyone can thrive at work and beyond. **Responsibilities** + ** Principal Physical Design , responsible for:** + Providing technical direction ... **Mixed-Signal IP** : Integrate complex analog IPs within a digital system, acting as a key interface between IP...Strong skills needed to coordinate with Register Transfer Level ( RTL ), Design for Testability (DFT), Computer-Aided … more
- Cadence Design Systems, Inc. (San Jose, CA)
- …of end-to-end design flow and tools for both analog and digital design from Architecture (schematics and RTL ) to GDS + MSEE preferred Key competencies + ... make an impact on the world of technology. Senior Principal Program Manager We are looking for a Senior...R&D Development Projects and Key Customer Engagements within the Design IP Group. The candidate must have solid, hands-on… more