- Arrow Electronics (San Jose, CA)
- **Position:** STA Engineer **Job Description:** POSITION SUMMARY * Proven experience in constraints (Func/Test) handling, block and top level static timing ... on Automation (Perl/Tcl/Awk/Python) * Able to provide technical guidance to Junior Engineer * Good in communication skill EDUCATION BACKGROUND A Bachelor's degree in… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …constraints, advanced OCV/SOCV concepts, derates, PBA timing, Distributed, Concurrent and Hierarchical STA flows. . Work efficiently with R&D and customer to enable ... basic understanding of Place and route, power analysis. Related tools/Keywords; PrimeTime, STA , Quantus #LI-MA1 The annual salary range for California is $100,100 to… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …to enable new and differentiating technologies.. + In this role, the Solutions Engineer (SE) is expected to work both independently and in collaboration with other ... team members to address customer issues and to identify new opportunities or Risk that are linked to those activities + The SE will interact with Product Engineering/RnD Team as well as Key Technologists at customer site to develop and enable new… more
- DoorDash (San Francisco, CA)
- …the foundation for decision-making at DoorDash. About the Role DoorDash is looking for a Sta ff Software Engineer ,Data to be a technical lead and help architect ... about you because + 8+ years of professional experience as a hands-on engineer and technical leader leading multiple projects + 6+ years experience working in… more
- Capgemini (San Francisco, CA)
- **Physical Design Engineer ** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip development, ... top-level PnR, CTS, block integration and ECO generation. *Expertise in timing closure ( STA ) of high frequency blocks *Handling blocks of high instance counts and… more
- Capgemini (San Francisco, CA)
- **Job Title : Senior ASIC Physical Design Engineer ** **Job Location: Santa Clara, CA (Hybrid)** **Key Responsibilities** + Chip level floor planning, partitioning, ... integration and ECO generation. + Expertise in timing closure ( STA ) of high frequency blocks + Handling blocks of...towards Intelligent Industry. Capgemini Engineering has more than 55,000 engineer and scientist team members in over 30 countries… more
- Broadcom (San Jose, CA)
- …Account, please Sign-In before you apply.** **Job Description:** The ASIC Design Engineer will need to interact internally with the Design Architect and externally ... to generate and understand timing reports Deep understanding of STA concepts - Solid understanding of RC networks and...and create timing diagrams Deep understanding of more advanced STA concepts - POCV/SOCV/LVF modeling of variation - MIS… more
- Broadcom (San Jose, CA)
- …desired PPA metrics. Candidate would also be required to do equivalence checks, STA , Timing closure and power optimization. Should be able to implement timing and ... time silicon. Primary expertise in place and route and/ or timing (constraints, STA ) can be considered for this position. Candidate should extremely proficient in… more
- Broadcom (San Jose, CA)
- …timing constraint file + RTL coding, Lint checks, CDC, Synthesis, Equivalency checking, STA , RTL/gate level simulations & silicon debug + Scripting for various IC ... design tasks such as STA , equivalency checks, test bench, simulations, synthesis, etc. + prepare block level resource requirements & development schedule + generate… more
- Cisco (San Jose, CA)
- …off checklist and reviews for chip tape out, including test coverage, STA . * Prior experience pre-silicon DFT implementation and verification flows, and post-silicon ... test bring up procedures. Preferred qualifications: * DFT CAD development - Test Architecture, Methodology and Infrastructure * Post silicon validation using DFT patterns. Why Cisco? #WeAreCisco, where each person is unique, but we bring our talents to work as… more
- Integense (San Jose, CA)
- …+ Experienced in all Front and Back End activities - RTL, Verification, Synthesis, STA , DFT, ATPG, etc. + Adept with System Verilog, C, and various scripting ... languages. + Experience with, implementing, designing with, and testing standard interfaces (I2C/SPI/APB/AHB). + Excellent English written and verbal communication skills. Preferred Qualifications + Experience implementing embedded microcontrollers. +… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …design flow. Experience with design tools such as Incisive/NCSim, Genus/Design Compiler, STA with Tempus/PrimeTime, power analysis. + Experience with Lint and CDC ... tool flows. + Exposure to some major IP and protocols, such as SERDES, PCIe and DDR4. + Self-driven. Good communication, organization, analytical, presentation and people skills. The annual salary range for California is $131,600 to $244,400. You may also be… more