- Cisco (San Jose, CA)
- … ASIC team can provide. You will work with exceptional talent with vast ASIC design and development expertise. With Cisco being a systems company, you will ... networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a...refining design and timing constraints for seamless physical design closure. As part of this… more
- Cisco (San Jose, CA)
- …You will work with outstanding talent and vast ASIC development expertise in design , DV, DFT, physical design , and post-silicon validation The team ... customer shipments. What You'll Do * You will participate in the ASIC design verification for Cisco high-end switching products. * Development of simulation… more
- Cisco (San Jose, CA)
- …team to address design bugs and close code coverage. * Work closely with physical design team to close design timing and place-and-route issues. * ... * Bachelor's degree in Electrical or Computer engineering and 12+ years of ASIC Design experience. * Verilog/System Verilog programming experience. * Interactive… more
- Cisco (San Jose, CA)
- …to address design bugs and close code coverage. * Work closely with the physical design team to close design timing and place-and-route issues. * Triage, ... Bachelor's Degree in Electrical or Computer Engineering with 7+ years of ASIC design experience or Master's Degree in Electrical or Computer Engineering with 4+… more
- Broadcom (San Jose, CA)
- … engineer capable of leading external and internal cross-functional teams in areas such as physical design , STA, DFT, and packaging? Have you taped out so many ... Candidate Account, please Sign-In before you apply.** **Job Description:** ** Senior Custom ASIC Engineering Lead** Are you...to prepare and execute risk mitigation actions + Execute physical design flows to check that incoming… more
- Cisco (San Jose, CA)
- …verification team to achieve coverage closure. * Collaborate with the verification and physical design teams to resolve block level issues. * Perform diagnostic ... Qualifications: * Bachelor's in Electrical or Computer engineering and 5+ years of ASIC Design experience or Master's degree in Electrical or Computer… more
- Cisco (San Jose, CA)
- …and correlation between PNR, Spice, and STA, along with advising the Physical Design team on best practices. *Additionally, you'll develop methodologies, ... for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers...guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive execution to ensure… more
- Cisco (San Jose, CA)
- …lead in San Jose, CA. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive high-quality DFT ... hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various… more
- Google (Mountain View, CA)
- …chip design tools. Minimum Qualifications: + At least 10 years experience in ASIC physical design flows and methodologies in advanced nodes. + Experience ... in a research environment. + Hands on experience and a solid understanding of ASIC physical design , physical design flows and methodologies including… more
- Capgemini (San Francisco, CA)
- …DV Engineer** **Job Location:** **San Francisco CA** **Job Description** We are seeking Senior Design Verification Engineer for our Full Time role with Capgemini ... tests, compile, and build hex code for processor tests. + Engage in design verification involving concurrency and simultaneous memory access. + Define and implement… more
- Broadcom (San Jose, CA)
- …and features as well as manage extremely large volumes of internet traffic. As a Senior Physical Design Engineer, the ideal candidate will be responsible for ... some of the most complex and cutting edge networking ASIC 's and multi-chip solutions to market over the last...power EM checks. . Methodology & Flow development of Physical Design and Timing Closure. . Interfacing… more
- Capgemini (South San Francisco, CA)
- …including strategic account development in complex semiconductor services sales, particularly in ASIC design services and sales pursuit management with at least ... aligned with customer product roadmaps. + We engage with senior management levels to strategize pursuits, develop account maps,...foundries, EDA companies, and IP providers. + Background in ASIC Design or Semiconductor Technology R&D is… more
- Capgemini (San Francisco, CA)
- …At least 5-8 years of experience in complex semiconductor services sales, particularly in ASIC design services. + Minimum of 5 years in Sales Pursuit Management. ... aligned with customer product roadmaps. + We engage with senior management levels to strategize pursuits, develop account maps,...foundries, EDA companies, and IP providers. + Background in ASIC Design or Semiconductor Technology R&D is… more
- Siemens (San Francisco, CA)
- …VHDL/Verilog/SystemVerilog or HLS using C++/systemC + 5+ years of proven hands-on experience in ASIC /FPGA design using RTL or HLS + Good understand of power, ... Req ID: 454002 Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop… more
- SLAC National Accelerator Laboratory (Menlo Park, CA)
- …resolving routine problems for scientist or engineers, independently. + Collaborate with senior engineers and scientists to design and develop special purpose ... oversee and manage instrumentation or system installation. + Ability to collaborate with senior engineering and scientific staff to design and develop special… more
- SLAC National Accelerator Laboratory (Menlo Park, CA)
- …open for designing the laboratory and operating the testing laboratory with senior scientists and collaborators from different companies. As a Computing Systems ... small-scale and large-scale algorithms running on different computing systems (CPU, GPU, ASIC , FPGA etc). These may include assessing the computing requirements for… more