• Senior ASIC Physical Design

    Capgemini (San Francisco, CA)
    **Job Title : Senior ASIC Physical Design Engineer ** **Job Location: Santa Clara, CA (Hybrid)** **Key Responsibilities** + Chip level floor planning, ... by Capgemini. **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior ASIC Physical Design Engineer_ **Location:** _CA-Santa Clara_ **Requisition… more
    Capgemini (10/16/24)
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  • Senior Asic Design

    Cisco (San Jose, CA)
    …* Bachelor's Degree in Electrical or Computer Engineering with 7+ years of ASIC design experience or Master's Degree in Electrical or Computer Engineering ... with 4+ years of ASIC design experience. * Prior experience working with Verilog or System Verilog programming skills * Experience with… more
    Cisco (01/11/25)
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  • Senior E/E & Semiconductor Engineer

    Capgemini (San Francisco, CA)
    **Physical Design Engineer ** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip ... **Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design ...**Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design Engineer_ **Location:** _CA-San Francisco_… more
    Capgemini (10/16/24)
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  • ASIC Design Verification…

    Cisco (San Jose, CA)
    …Bachelor's Degree in EE, CE, or other related field. * 7+ years of related ASIC design verification experience. * Proficient in ASIC verification using ... design in emulation. * Oversee and manage the ASIC bring-up process. Who You Are The Core Hardware...Business Unit is on the lookout for a driven Senior Verification Engineer to join us in… more
    Cisco (12/31/24)
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  • ASIC Engineer

    Cisco (San Jose, CA)
    …/lead to engage in new development of our UCS family. You will have an ASIC design and verification background with hands-on experience in RTL verification and ... for ASIC bring up Minimum Qualifications * 8+ years ASIC design verification experience with Bachelor's or Master's degree in equivalent experience. *… more
    Cisco (12/31/24)
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  • Sr Architect - ASIC

    GE HealthCare (Palo Alto, CA)
    …(MR) systems? Join our innovative MR Hardware Team as a Lead Electrical Engineer - Wireless and be at the forefront of developing state-of-the-art wireless modules ... and interfaces! About the Role: As a Lead Electrical Engineer - Wireless, you will play a pivotal role...wireless solutions within MR systems. You will collaborate with senior technical team members to deliver groundbreaking designs for… more
    GE HealthCare (10/20/24)
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  • Senior Design Verification (DV)…

    Cisco (San Jose, CA)
    …being developed in the industry. What You'll Do You will participate in the ASIC design verification and Emulation for Cisco high-end switching products. One of ... and Wireless products. With approximately 2,100 employees across 16 countries, we design the networking hardware for Enterprises and Service Providers of various… more
    Cisco (01/07/25)
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  • Senior E/E & Semiconductor Engineer

    Capgemini (San Francisco, CA)
    **Job Role:** **Physical Design (Synthesis) Engineer ** **Job Location : San Jose CA** **Job Description** + At least 7 years of experience in ASIC /SOC ... _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - Physical Design (Synthesis) Engineer_ **Location:** _CA-San… more
    Capgemini (11/12/24)
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  • Senior Digital Design

    Teledyne (Mountain View, CA)
    …for current and emerging challenges. Teledyne Microwave Solutions is hiring a Digital Design Engineer that will be responsible for the digital design ... development and service issues + Advanced level experience with digital and ASIC design + Advanced level experience with RISC or ARM-based microcontrollers +… more
    Teledyne (01/08/25)
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  • Senior Physical Design

    Broadcom (San Jose, CA)
    …and features as well as manage extremely large volumes of internet traffic. As a Senior Physical Design Engineer , the ideal candidate will be responsible for ... some of the most complex and cutting edge networking ASIC 's and multi-chip solutions to market over the last...EM checks. . Methodology & Flow development of Physical Design and Timing Closure. . Interfacing with internal and… more
    Broadcom (11/27/24)
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  • Senior Silicon Digital Design

    Google (Mountain View, CA)
    design concepts, and languages such as Verilog or SystemVerilog. + Experience with ASIC design methodologies for clock domain checks, reset checks and low ... practical experience. + 5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog. + 5… more
    Google (12/10/24)
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  • COPD (Customer Owned Physical Design

    Broadcom (San Jose, CA)
    …that keep the globe connected. Our ASIC products division is looking for senior , physical design engineering veterans to guide teams designing some of the ... Technical Lead for Physical Designs Are you a versatile, senior engineer capable of leading external and... design verification and sign-off. 6. Knowledge of ASIC design flow including physical design more
    Broadcom (11/28/24)
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  • Senior E/E & Semicon Engineer

    Capgemini (San Jose, CA)
    **Job Role: Senior ** **Performance Modeling Engineer ** **Job Location: San Jose CA** **Job description:** We are seeking a highly skilled candidate with a strong ... candidate will have a deep understanding of System-on-Chip (SoC) design and architecture, as well as Expertise in performance...+ Experience with Synopsys or Cadence EDA tools and ASIC /SOC Power Analysis Tools. + Deep understanding of SoC… more
    Capgemini (11/14/24)
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  • Senior Software Engineer

    Cisco (San Jose, CA)
    …close on 02/06/2025 Who We Are Cisco Silicon One is the center of Cisco's ASIC design and is driving the development of next-generation network devices for the ... within a stable and leading corporate environment, and our design center hosts all silicon Hardware and Software development...design teams to define the next generation of ASIC products being developed Minimum Qualifications * BS/BA with… more
    Cisco (01/07/25)
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  • Principal Software Engineer - Silicon One

    Cisco (San Jose, CA)
    Who We Are Cisco Silicon One is the center of Cisco's ASIC design and is driving the development of next-generation network devices for the 5G and AI era. Our ... design teams to define the next generation of ASIC products being developed. You will work cross-functionally with...Engineer . * Experience in building software stack for ASIC or similar network processors. * Ability to constantly… more
    Cisco (12/05/24)
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  • Senior Hardware Engineer

    quadric.io, Inc (Burlingame, CA)
    …to get in on the ground floor of a revolutionary new processor architecture. As a senior member of our chip design team, you will contribute to all stages of ... or Computer Engineering with a minimum of five years of CPU/GPU/ ASIC front-end design + Proficiency in SystemC, SystemVerilog, or Verilog + Strong background… more
    quadric.io, Inc (12/10/24)
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  • Senior DFT Engineer

    Cisco (San Jose, CA)
    …hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various ... be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with...in San Jose, CA with a primary focus on Design -for-Test. You will work with Front-end RTL teams, backend… more
    Cisco (10/17/24)
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  • IC Package Mechanical FEA Engineer (R&D)

    Broadcom (San Jose, CA)
    …and electrical performance, etc.. **RESPONSIBILITIES:** + Design responsibility for mechanical design aspects of ASIC packages + Use advanced FEA to quantify ... + Create presentations for and present to various audiences : engineers, managers, senior management, customers, and vendors + Document design rules and… more
    Broadcom (11/01/24)
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  • Hardware Engineer 2

    Microsoft Corporation (Mountain View, CA)
    …performance monitors and post-silicon SOC power and performance tuning. + Familiarity with ASIC power analysis, low power design and power optimization. + ... Microsoft's current and future on-line services. We are looking for a **Hardware** ** Engineer II** to join the System Architecture team focusing on power and… more
    Microsoft Corporation (01/10/25)
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  • Sr Sales Executive Semiconductor Engineering…

    Capgemini (San Francisco, CA)
    …At least 5-8 years of experience in complex semiconductor services sales, particularly in ASIC design services. . Minimum of 5 years in Sales Pursuit Management. ... needs aligned with customer product roadmaps. . Engage with senior management levels to strategize pursuits, develop account maps,...foundries, EDA companies, and IP providers. . Background in ASIC Design or Semiconductor Technology R&D is… more
    Capgemini (12/25/24)
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