- Microsoft Corporation (Mountain View, CA)
- …and efficient methods to detect hardware/software vulnerabilities. The team is seeking a ** Senior Design Verification Engineer ** to deliver ... SoC Design Verification team is seeking a **Principal Design Verification Engineer ** who can work with cross-discipline teams (including systems,… more
- Google (Mountain View, CA)
- …in SoCs. + Experience in Advanced RISC Machine (ARM) and RISC-V processor based Design Verification including tool chains and C based testing. + Experience in ... low-power design verification . Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's… more
- quadric.io, Inc (Burlingame, CA)
- …progress on verification Requirements + At least 5 years of experience in design verification for CPU or GPUs. + Deep knowledge of leading verification ... Collaborate with architects, HW & SW designers to document verification test plans + Implement testbenches using commercial VIPs...drivers, assembly or C++ programs to efficiently test the design + Use coverage metrics to track and communicate… more
- Google (Mountain View, CA)
- …Science, with an emphasis on computer architecture. + Experience in low-power design verification . + Experience with Universal Verification Methodology ... and coverage, and ensure documentation is easy to use. + Perform design verification for future CPU developments. + Perform functional verification and… more
- Cisco (San Jose, CA)
- …Who You Are The Core Hardware Business Unit is on the lookout for a driven Senior Verification Engineer to join us in developing the next generation of ... in EE, CE, or other related field. * 7+ years of related ASIC design verification experience. * Proficient in ASIC verification using UVM/System Verilog. *… more
- Capgemini (San Francisco, CA)
- **Physical Design Engineer ** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip ... Timing with SI and OCV, Power, IR and Physical Verification at both block and chip level *Understanding constraints...**Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design Engineer_ **Location:**… more
- Capgemini (San Francisco, CA)
- **Job Title : Senior ASIC Physical Design Engineer ** **Job Location: Santa Clara, CA (Hybrid)** **Key Responsibilities** + Chip level floor planning, ... Timing with SI and OCV, Power, IR and Physical Verification at both block and chip level + Understanding...block and chip level + Understanding constraints and fixing design /timing techniques + Block level implementation from netlist to… more
- Capgemini (San Francisco, CA)
- **Job Role:** **Physical Design (Synthesis) Engineer ** **Job Location : San Jose CA** **Job Description** + At least 7 years of experience in ASIC/SOC project ... _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - Physical Design (Synthesis) Engineer_ **Location:** _CA-San… more
- Ford Motor Company (Palo Alto, CA)
- …and growth through electric and connected vehicles and services. The Power Electronics Design Engineer will own complex drive unit inverter sub-components from ... / test equipment. + Plan, coordinate, and execute test campaigns for design verification of inverter sub-components and the inverter system. + Optimize costs… more
- Broadcom (San Jose, CA)
- …and features as well as manage extremely large volumes of internet traffic. As a Senior Physical Design Engineer , the ideal candidate will be responsible for ... . Physical implementation of blocks and top-level including clock-tree. . Physical verification and timing closure for block and chip-level. . Static and dynamic… more
- Teledyne (Mountain View, CA)
- …for current and emerging challenges. Teledyne Microwave Solutions is hiring a Digital Design Engineer that will be responsible for the digital design ... module interfaces, conducts design reviews, and participates in design implementation. Responsibilities include debugging, verification , and resolving… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …for front-end coding, scripting and developing flows at all phases of the digital design and functional verification . It is further expected that the candidate ... + Digital microarchitecture definition and documentation + RTL logic design , debug and functional verification + IP integration and verification + Familiar… more
- Power Integrations (San Jose, CA)
- As a Senior Staff IC Design Engineer , you will be responsible for switching power supply development of integrated circuits using CMOS/Bipolar analog/digital ... circuitry. Specific responsibilities are: + Mixed-mode integrated circuit design for switching power supply: + Simulation with Cadence tools. + Layout supervision… more
- Cisco (San Jose, CA)
- …those ASICs more general and programmable. Cisco Common ASIC Group is looking for a Senior ASIC Verification Engineer to drive existing projects and engage ... Who You Are: You are a talented, motivated ASIC verification engineer to join the team and... of very complex ASICs. You will have a Design Verification background, and hands-on experience in… more
- Microsoft Corporation (Mountain View, CA)
- …high-performance Azure cloud servers, clients, and augmented reality. We are looking for a ** Senior ** **Silicon** ** Design Engineer ** to work on leading edge ... of custom IP blocks, working with a group of other design team members, design verification engineers, and architects. Individuals will be working… more
- Power Integrations (San Jose, CA)
- …using CMOS/Bipolar analog/digital circuitry. Technical responsibilities include: circuit design (mostly digital, some analog), simulation, layout supervision and ... verification , preparation of test plan for the test group,...and requires having good verbal and written communications skills. Engineer must be interested in learning, be a creative… more
- Siemens Digital Industries Software (Fremont, CA)
- …**Req ID:** 446255 Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to ... the increasingly complex world of chip, board, and system design . We are seeking a passionate and highly skilled...We are seeking a passionate and highly skilled software engineer to join the Questa Visualizer Debug R&D team… more
- Google (Mountain View, CA)
- …field, or equivalent practical experience. + 5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or ... techniques to optimize RTL code, performance and power as well as low-power design techniques. + Experience with scripting languages like Perl or Python. Preferred… more
- City and County of San Francisco (San Francisco, CA)
- …the minimum qualifications. Application Deadline: Continuous How to Apply: Applications for Senior Information Systems Engineer - Networks Specialty are only ... components that integrate these systems together as an enterprise networking backbone. The 1043 Senior Networks Engineer is the advanced journey level in the … more
- City and County of San Francisco (San Francisco, CA)
- …the minimum qualifications. Application Deadline: Continuous How to Apply: Applications for Senior Information Systems Engineer - Applications Specialty are only ... that integrate these systems together as an enterprise networking backbone. The 1043 Senior Applications Engineer is the advanced journey level in the … more