- Google (Fremont, CA)
- …and visualization with commonly used tools like JMP, Reliasoft, etc. As a Silicon Reliability Engineer , you will be responsible for developing and continuously ... closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR)...analysis/reporting, and manage stress schedules for the microLED backplane silicon . + Work with Design -for-Test (DFT) and… more
- Cisco (San Jose, CA)
- …Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities. What You'll Do You will be part of ... -for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture... physical implementation from RTL to GDSII. As Physical Verification Engineer your main responsibilities will… more
- Google (Mountain View, CA)
- …actionable feedback to silicon design engineers and architects for design improvements. + Participate in establishing physical design methodologies, ... who are willing to help out with whatever moves silicon design and architecture forward. We regularly...design options. + Drive architectural feasibility studies, explore RTL/ design tradeoffs for physical design … more
- Cisco (San Jose, CA)
- …talent and vast ASIC development expertise in design , DV, DFT, physical design , and post- silicon validation The team comprises micro-architects, ... We Are The Common Hardware Group (CHG) delivers the silicon , optics, and hardware platforms for Cisco's core Switching,...You'll Do * You will participate in the ASIC design verification for Cisco high-end switching products. * Development… more
- Cisco (San Jose, CA)
- …and guide them in refining design and timing constraints for seamless physical design closure. As part of this team, you'll contribute to developing ... first customer shipments. Your Impact You are a diligent Design /SDC Engineer with strong analytical skills and... team who oversees fullchip SDCs and works with physical design and DFT teams to close… more
- Cisco (San Jose, CA)
- …team to address design bugs and close code coverage. * Work closely with physical design team to close design timing and place-and-route issues. * ... CA 4+ days/week. Meet the Team Join the Cisco Silicon One team in developing a unified silicon...You will work with exceptional talent with vast ASIC design and development expertise. With Cisco being a systems… more
- Cisco (San Jose, CA)
- …verified. You will work closely with Back-end team on timing signoff for seamless physical design closure. You will also collaborate with the System and Software ... are received. Meet the Team The Common Hardware Group (CHG) delivers silicon , optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless… more
- Cisco (San Jose, CA)
- …team to address design bugs and close code coverage. * Work closely with physical design team to close design timing and place-and-route issues. * ... requires being onsite in San Jose, CA 4+ days/week. Meet the Team Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and… more
- Cisco (San Jose, CA)
- …to address design bugs and close code coverage. * Work closely with the physical design team to close design timing and place-and-route issues. * Triage, ... San Jose, CA. Meet the Team Join the Cisco Silicon One team in developing a unified silicon...Electrical or Computer Engineering with 7+ years of ASIC design experience or Master's Degree in Electrical or Computer… more
- Cisco (San Jose, CA)
- …verification team to achieve coverage closure. * Collaborate with the verification and physical design teams to resolve block level issues. * Perform diagnostic ... San Jose office 4+ days/week. Meet the Team Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon...Electrical or Computer engineering and 5+ years of ASIC Design experience or Master's degree in Electrical or Computer… more
- Broadcom (San Jose, CA)
- …Account, please Sign-In before you apply.** **Job Description:** **Job Description: IC Design Engineer ** + Participate in IP level architectural definition ... team on test plan development, debugging, and coverage closure + Collaborate with physical design team on constraint generation, timing closure analysis, formal… more
- Capgemini (San Francisco, CA)
- …** **Job Location:** **San Francisco CA** **Job Description** We are seeking Senior Design Verification Engineer for our Full Time role with Capgemini ... in collaboration with the Design team. + Collaborate with multi-functional teams ( Design , Model, Emulation, and Silicon validation) to ensure the highest … more
- Skyworks (San Jose, CA)
- Power Amplifier/RFIC Design Engineer Apply now " Date:Mar 11, 2025 Location: San Jose, CA, US Company: Skyworks If you are looking for a challenging and exciting ... professional for the role of Principal Power Amplifier/RF IC Design Engineer at our San Jose Office,...at our San Jose Office, at the heart of Silicon Valley, CA. Skyworks is an innovator of high-performance… more
- Google (Mountain View, CA)
- …functionality of the design . + Provide input on synthesis, timing closure, and Physical Design of digital blocks. + Take a leadership role on technical ... experience. + 5 years of experience with digital logic design principles, RTL design concepts, and languages...part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer… more
- Meta (Menlo Park, CA)
- …considering Input/Output Physical Layer (IO PHY), SI/PI and physical design . **Minimum Qualifications:** Minimum Qualifications: 10. Bachelor's degree ... process 25. Experience in collaborating with cross-functional teams, including chip top design , physical design , Static Timing Analysis (STA), package,… more
- Broadcom (San Jose, CA)
- … design trade-offs. You will collaborate closely with verification engineers and physical design teams to ensure functional correctness, timing closure, and ... is a leader in semiconductor innovation, delivering cutting-edge custom silicon solutions for AI, networking, HPC among many other...and Timing Closure:** + Perform synthesis and work with physical design teams to achieve timing closure… more
- Google (Mountain View, CA)
- …+ Work with the Verification team to ensure production of quality designs, and the physical design and power teams to meet frequency, power, and area goals. + ... experience. + 10 years of experience with digital logic design principles, RTL design concepts, and languages...part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …to integrating such high power devices into complex scalable enterprise grade hardware. The design / verification / physical design of these ASICs pushes ... is an industry leading emulation platform used for emulating complex custom silicon designs used by top semiconductor industries globally . The Palladium platform… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …on Chip, CPU Cores & DSP, and Vision Cores. The intern will work with the Physical Design CAD team and R&D to adopt latest capabilities to optimize the PPA ... to make an impact on the world of technology. The Cadence Silicon Solutions Group (SSG) develops industry-leading Digital IP (Intellectual Property), from RISC-V… more
- Google (Mountain View, CA)
- …with the Functional Verification team to ensure production quality designs, and with the Physical Design team to meet frequency, power, and area goals. Google is ... Engineering, Computer Science or equivalent practical experience. + Experience with digital logic design principles, RTL design concepts, and use of Verilog or… more