- Microsoft Corporation (Mountain View, CA)
- …related to Microsoft cloud hardware. We are looking for a Senior Design Verification Engineer for customer focused solutions, insight and industry knowledge to ... and optimize the Cloud infrastructure. We are looking for a Senior Design Verification Engineer to join the team. **Responsibilities** In this role you will: +… more
- Arrow Electronics (Mountain View, CA)
- **Position:** Design Verification Engineer **Job Description:** Principal Accountabilities * Responsible for architecting Verification Environment for ASIC ... SoC and providing verification support from defining verification plan to multi-million gate product tapeout & for Test design and development * Develop complex… more
- Broadcom (San Jose, CA)
- …you apply.** **Job Description:** Broadcom is looking for a senior level Digital Design Verification engineer . In this highly visible role you will be working on ... Engineering with 10+ years of experience in digital design verification + Hands on experience in SV UVM, SV...Hands on experience in SV UVM, SV RNM and verification coverage matrix + Prior experience in processor … more
- Microsoft Corporation (Mountain View, CA)
- …will manage and optimize the Cloud infrastructure. We are looking for a **Senior Verification Engineer ** to join the team. **Responsibilities** The role will be ... responsible for pre-silicon functional verification , creation of verification environments and tests at the block and sub-system level, reference modeling,… more
- Broadcom (San Jose, CA)
- …Jose, California Development Center. We are seeking a highly skilled HBM and SerDes DFT Verification Engineer to join our dynamic team. In this role, you will ... before you apply.** **Job Description:** Broadcom's ASIC Product Division is seeking candidates for HBM/DDR/SERDES Verification Lead Engineer position at our San… more
- Broadcom (San Jose, CA)
- …team responsible for state-of-the-art subsystem development to meet customer requirements. The engineer will be responsible for a variety of advanced verification ... tasks such as: verification environment development using modern verification techniques (System Verilog and UVM); designing verification components such as… more
- Ford Motor Company (Palo Alto, CA)
- …connected vehicles and services. As a Senior System Software Integration and Validation Engineer , you will play a critical role in ensuring the quality and ... automotive systems. You will be responsible for designing, developing, and executing verification and validation activities to ensure that our software meets the… more
- Broadcom (San Jose, CA)
- …custom AI chips. This position is responsible for IP and subsystem verification , including SerDes and processor subsystem among many other IPs. **Requirements:** * ... Experience in architecting modern verification environment and test benches * Deep understanding and...benches * Deep understanding and knowledge of industry standard verification methodologies and tools * Hands on and In-depth… more
- Broadcom (San Jose, CA)
- …and develop scalable and reusable Testbench environment using the framework of Verification Methodologies. + Drive Test plans for all features for Block/Core/SOC and ... and get to full Functional coverage and bring the Verification to closure + Debug Regression failures, analyze Functional...in an efficient way. + Lead the documentation of verification strategy including Test plans, Verification Environment,… more
- quadric.io, Inc (Burlingame, CA)
- …processors + Collaborate with architects, HW & SW designers to document verification test plans + Implement testbenches using commercial VIPs and/or internal SW ... Use coverage metrics to track and communicate progress on verification Requirements + At least 5 years of experience...+ At least 5 years of experience in design verification for CPU or GPUs. + Deep knowledge of… more
- Cisco (San Francisco, CA)
- …contribute to system and processor architecture, high-speed logic design and verification , digital signal processing, memory and custom library development, physical ... timing closure. **Preferred Qualifications** ** ** + Experience with ASIC verification methodologies (eg, UVM, SystemVerilog) + Understanding of physical design and… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …who want to make an impact on the world of technology. Principal Software Engineer - Low-Power Verification (Palladium & Protium) We are seeking a highly ... skilled Senior Software Engineer to help build the next generation of low-power verification software for the Palladium and Protium emulation platforms. In this… more
- Micron Technology, Inc. (San Jose, CA)
- …large language models (LLMs) for the purpose of automated Silicon design and Design Verification (DV). The engineer is expected to build LLM based EDA workflows ... quality. **Responsibilities:** + Develop LLM applications to automate electronics design and verification . + Optimize and fine-tune LLMs for the purpose of automated… more
- Broadcom (San Jose, CA)
- …Account, please Sign-In before you apply.** **Job Description:** ASIC/Layout Design Engineer : Oversees definition, design, verification , and documentation for ... and block pin assignment. + Perform blocks PnR, timing closure, physical verification . + Perform blocks IR/EM analysis. Experience with chip level IR/EM analysis… more
- Abbott (Alameda, CA)
- …female executives, and scientists. **The Opportunity** The Sr Staff Embedded Software Engineer leads the development, verification , ensuring timely delivery and ... to support. **What you'll work on** + Lead software development, verification , and validation for embedded biowearable products, ensuring on-time delivery within… more
- City and County of San Francisco (San Francisco, CA)
- …Deadline: Continuous How to Apply: Applications for Journey Information Systems Engineer - Security Specialty are only accepted through an online process. ... together as an enterprise networking backbone. The 1042 Security Engineer is the journey level position in the ...Trainee Program may be substituted for the required degree. Verification : Applicants may be required to submit verification… more
- City and County of San Francisco (San Francisco, CA)
- …Application Deadline: Continuous How to Apply: Applications for Senior Information Systems Engineer - Networks Specialty are only accepted through an online process. ... as an enterprise networking backbone. The 1043 Senior Networks Engineer is the advanced journey level in the ...Trainee Program may be substituted for the required degree. Verification : Applicants may be required to submit verification… more
- City and County of San Francisco (San Francisco, CA)
- …Deadline: Continuous How to Apply: Applications for Assistant Information Systems Engineer - Systems Specialty are only accepted through an online process. ... enterprise networking backbone or platform. The 1041 Assistant Systems Engineer is the entry level in the Engineer...Trainee Program may be substituted for the required degree. Verification : Applicants may be required to submit verification… more
- City and County of San Francisco (San Francisco, CA)
- …Deadline: Continuous How to Apply: Applications for Journey Information Systems Engineer - Applications Specialty are only accepted through an online process. ... together as an enterprise networking backbone. The 1042 Applications Engineer is the journey level position in the ...Trainee Program may be substituted for the required degree. Verification : Applicants may be required to submit verification… more
- City and County of San Francisco (San Francisco, CA)
- …safely, and comply with all applicable safety rules and regulations. STATIONARY ENGINEER POSITION AND JOB RESPONSIBILITIES + Operates, maintains and repairs a wide ... of organisms in water. Experience: Four (4) years of verified journey-level stationary engineer experience in the maintenance, repair and operation of a variety of… more