- Google (Sunnyvale, CA)
- Physical Design Flow and Methodology Lead _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Advanced** Experience owning outcomes and decision making, ... equivalent practical experience. + 8 years of experience with physical design flow and methodologies....a team that is transitioning to a new chip design methodology , giving you the opportunity to… more
- Google (Sunnyvale, CA)
- …+ Experience leading one or more aspects of physical design or physical design flow / methodology , to successful tape-outs and shipping silicon. + ... Experience in extraction of design parameters, QoR metrics, and analyzing data trends. +...systems. In this role, you will work on the physical implementation of Application-specific integrated circuits (ASIC) using advanced… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ASIC Physical Design Methodology /CAD Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where ... goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN METHODOLOGY /CAD ENGINEER (SILICON...best-in-class PPA and run times + Create integrated hierarchical physical design flow to enable… more
- Amazon (Cupertino, CA)
- …is possible today. Key job responsibilities - You will create and support innovative physical design methodology and CAD flows. - Develop cloud ... infrastructure to support physical design work. - Drive improvement in RTL2GDS flows/...- Proven track record of delivering metric driven PPA flow development and support. Preferred Qualifications - Demonstrated level… more
- Amazon (Cupertino, CA)
- …massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new ... and efficiencies. Be able to independently troubleshoot digital tool flow usage and deploy solutions; Fluent in scripting languages...MS + 7yrs in EE/CS - 5+ years developing physical design methodology or CAD… more
- NVIDIA (Santa Clara, CA)
- …and SOCs, with emphasis on PPA (Power, Performance, Area) and runtime improvement of the physical design flow on advanced technology nodes + Develop flows ... to amplify human inventiveness and intelligence. What you will be doing: + Developing innovative physical design methodologies for implementation of GPU, CPU… more
- NVIDIA (Santa Clara, CA)
- …aging, self-heating, thermal impact, IR drop etc. + Collaborate with technology leads, VLSI physical design , and timing engineers to define and deploy the most ... and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the...cells/memory/IO IP modeling and its usage in the ASIC flow . Hands-on experience in advanced CMOS technologies, design… more
- NVIDIA (Santa Clara, CA)
- …Power Integrity Methodology Engineer. What you'll be doing: + Developing physical design methodologies for rail analysis and signoff. + Responsible for ... Engineering or related field. + Minimum 5+ years of experience in IR/EM/Thermal flow methodology development and support. + Strong understanding of all aspects… more
- NVIDIA (Santa Clara, CA)
- …aging, self-heating, thermal impact, IR drop etc. + Collaborate with technology leads, VLSI physical design , and timing engineers to define and deploy the most ... human inventiveness and intelligence. We are seeking an innovative Timing Methodology Engineer to help drive multi-physics sign-off strategies for the world's… more
- NVIDIA (Santa Clara, CA)
- …related fields (or equivalent experience). + 8+ years of experience in logic design implementation and/or physical design implementation + Deep understanding ... and relative area, timing, and power trade-offs + Strong understanding of physical design implementation eg: physical synthesis, placement, routing,… more
- Meta (Sunnyvale, CA)
- …nodes 2. Resolve design and flow issues related to the physical design , identify potential solutions, and drive execution 3. Deliver physical ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure...TCL, Python, Perl or Shell 16. Knowledge of RTL2GDSII flow and design tape-outs in 5nm or… more
- SpaceX (Sunnyvale, CA)
- …engineering, computer engineering or computer science + 5+ years of ASIC and/or physical design flow development experience in industry PREFERRED SKILLS ... with clock domain crossings, DFT/Scan/MBIST/LBIST/JTAG/Boundary-scan testing and understanding impacts on physical design flow + Experience with high… more
- Broadcom (San Jose, CA)
- …and Route + Clock Tree Synthesis + Floor-planning and Layout + Flow and Methodology Development + Collaborating with IC Design RTL Engineers + Must work in ... this position will require in-depth knowledge and expertise in all Physical Design aspects of taking RTL to silicon tape-out. **Responsibilities include, but… more
- NVIDIA (Santa Clara, CA)
- …timing paths through ECOs including crosstalk and noise analysis. + Expertise in physical design and optimization eg, placement, routing, cell sizing, buffering, ... modeling and converging considering process variations. + Experience in methodology and/or flow development as well as automation. NVIDIA is widely considered… more
- NVIDIA (Santa Clara, CA)
- …from the crowd: + Proven ownership and hands-on experience across the entire silicon design flow , from micro-architecture and RTL design to back-end ... clocking, and power management solutions. + You'll drive the design and physical implementation of custom digital...layout delivery. + Integrate AI/ML techniques directly into the design process and methodology . + Be a… more
- NVIDIA (Santa Clara, CA)
- …Analysis, Power and Noise Analysis, Silicon Instrumentation and Measurement + CAD and Physical Design Methodologies ( Flow and Tool s Development), Chop ... interest in one of our 202 6 Hardware ASIC Design Internships. We'll review resumes on an ongoing basis,...P&R and Timing Closure + Performance, Verification, and Emulation Methodology Depending on the internship role, prior experience or… more
- Broadcom (San Jose, CA)
- …and power optimization. + Implement timing and functional ECOs. + Apply Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous ... Sign-In before you apply.** **Job Description:** **Responsibilities Include:** + Work on Design Implementation activities related to place and route and/ or timing… more
- Broadcom (San Jose, CA)
- …timing and functional ECOs. In this role, the candidate will apply Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous ... before you apply.** **Job Description:** Candidate would be required to work on Design Implementation activities related to place and route and/ or timing closure -… more
- Broadcom (San Jose, CA)
- …+ Hierarchical DFT Flow and Methodology Development + Collaborating with IC Design RTL Engineers and Physical Design Engineers + Must work in person ... **Job Description:** Broadcom is searching for a DFT IC Design Engineer to join the Data Center Solutions Group....knowledge and expertise towards DFT related aspects of IC Design through RTL and netlists. **Responsibilities include, but are… more
- Broadcom (San Jose, CA)
- …members of this team. + In this role, the candidate will apply Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous criteria ... you apply.** **Job Description:** Candidate would be required to work on Design Implementation activities related to complex digital and mixed signal IP blocks… more