• Senior ASIC Test

    NVIDIA (Santa Clara, CA)
    …life's work, to amplify human inventiveness and intelligence. We are now looking for a motivated Senior ASIC Test Timing Engineer to join our dynamic and ... inventiveness and intelligence. What you'll be doing: + Drive timing analysis and closure of Nvidia's GPUs, CPUs, DPUs...DFX, Clocks, and other teams in coming up with timing closure strategy, creating timing constraints, driving… more
    NVIDIA (10/07/25)
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  • Senior ASIC Engineer - SDC

    Cisco (San Jose, CA)
    **Sr. ASIC Engineer** The application window is expected to close on 1/26/2026. The job posting may be removed earlier if the position is filled or if a sufficient ... service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon… more
    Cisco (12/03/25)
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  • Sr. SOC/ ASIC Physical Design Engineer…

    SpaceX (Sunnyvale, CA)
    Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the ... ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're...internet to millions of users worldwide. We design, build, test , and operate all parts of the system -… more
    SpaceX (12/07/25)
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  • Senior ASIC Design Engineer - DFX

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior ASIC Design Engineer - DFX NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked ... imagination and intelligence. Make the choice to join us today. Design-for- Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative… more
    NVIDIA (10/25/25)
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  • Sr. SOC/ ASIC DFT Engineer (Silicon…

    SpaceX (Sunnyvale, CA)
    …path delay fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows. + Run and debug non- timing and SDF annotated gate-level ... Sr. SOC/ ASIC DFT Engineer (Silicon Engineering) Sunnyvale, CA Apply...internet to millions of users worldwide. We design, build, test , and operate all parts of the system -… more
    SpaceX (12/07/25)
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  • Sr. ASIC Design Engineer, Cloud-Scale…

    Amazon (Cupertino, CA)
    …scale and rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ... signal routing - As a key member of the ASIC design team, you will implement and deliver high...requirements. - Develop micro-architecture, implement SystemVerilog RTL, and deliver synthesis/ timing clean design with constraints. - Perform lint and… more
    Amazon (11/20/25)
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  • Sr. SOC/ ASIC Physical Design…

    SpaceX (Sunnyvale, CA)
    Sr. SOC/ ASIC Physical Design Methodology/CAD Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is ... ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN METHODOLOGY/CAD ENGINEER (SILICON ENGINEERING) At SpaceX...internet to millions of users worldwide. We design, build, test , and operate all parts of the system -… more
    SpaceX (12/07/25)
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  • Senior DFT Static Timing Analysis…

    Google (Sunnyvale, CA)
    Senior DFT Static Timing Analysis Engineer, Cloud _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving problems, and ... and associated test methodologies. + Experience in Tessent generated DFT timing constraints, SSN bus networks and constraints and mode merging. + Experience with… more
    Google (12/05/25)
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  • Senior Silicon Bringup and Test

    Google (Fremont, CA)
    Senior Silicon Bringup and Test Lead, Raxium _corporate_fare_ Google _place_ Fremont, CA, USA **Advanced** Experience owning outcomes and decision making, ... + 15 years of experience in Application-Specific Integrated Circuit/System on Chip ( ASIC /SoC) design, with a focus on both digital logic design and Design… more
    Google (11/22/25)
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  • Senior Principal DFT Design Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …of professional experience in SoC/ ASIC Digital Design with focus on Design for Test (DFT) + Should possess intimate knowledge of DFT insertion flows + Basic scan ... on the world of technology. We are looking for SoC/ ASIC Digital Design Engineer with experience in Design for... Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan… more
    Cadence Design Systems, Inc. (10/30/25)
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  • Sr. Full Chip Physical Design Engineer (Silicon…

    SpaceX (Sunnyvale, CA)
    …is providing fast, reliable internet to millions of users worldwide. We design, build, test , and operate all parts of the system - thousands of satellites, consumer ... cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing… more
    SpaceX (11/14/25)
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