- Google (Sunnyvale, CA)
- Senior DFT Static Timing Analysis Engineer, Cloud _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving ... equivalent practical experience. + 5 years of experience in static timing (ie, full chip timing...and associated test methodologies. + Experience in Tessent generated DFT timing constraints, SSN bus networks and… more
- NVIDIA (Santa Clara, CA)
- …2+ years' experience in Timing and STA + Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing ... and intelligence. We are now looking for a motivated Senior ASIC Test Timing Engineer to join...Understanding of DFT logic and experience with DFT timing closure for various modes eg,… more
- NVIDIA (Santa Clara, CA)
- …experience in Synthesis and Timing + Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and ... or SOCs. + Understanding of DFT logic and experience with DFT timing closure for various modes eg, scan shift and capture, transition faults, BIST,… more
- Google (Fremont, CA)
- …Testability ( DFT ) implementation. + Experience with industry-standard EDA tools for synthesis, Static Timing Analysis (STA), and DFT . + Experience with ... Senior Silicon Bringup and Test Lead, Raxium _corporate_fare_...advanced DFT techniques such as hierarchical DFT , compression, and diagnosis. + Proficiency in hardware description… more
- NVIDIA (Santa Clara, CA)
- …at project execution and/or flow development. + Strong experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and ... and intelligence. We are now looking for a motivated Senior ASIC Physical Design Engineer, Netlisting to join our...hands-on debugging capability and problem-solving skills. + Background in DFT timing closure for various modes eg… more
- Cisco (San Jose, CA)
- …DC/DCG/FC), Verilog/System Verilog programming. **Preferred Qualifications** + Experience in Static Timing Analysis. + Experience with constraint analyzer ... design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes. + Option to also do… more
- NVIDIA (Santa Clara, CA)
- …ADC etc. + Hands on experience running Spice simulations, EM/IR analysis, and static timing analysis/closure + Experience with spice simulation for noise ... We are now looking for a motivated Senior Circuit Design Engineer to join our dynamic...challenging and exciting role in improving the netlist and timing quality of our designs and if you are… more
- Microsoft Corporation (Mountain View, CA)
- …across front-end areas like RTL & VIP Design, Design Verification, Validation, DFT , Emulation, Design Synthesis, RTL Power Anaysis, PD Handoff and SoC integration. ... so that they can deliver cutting-edge silicon solutions for Microsoft. As a Senior Front-End CAD Engineer, you'll drive the development and adoption of cutting-edge… more
- SpaceX (Sunnyvale, CA)
- … budgeting and constraint pushdown to partition owners + Work with static timing analysis, physical verification, electromigration/voltage drop, noise and other ... bus routing, sequential pipeline planning and top level design for testability ( DFT ) planning + Collaborate with chip architects, ASIC engineers, package engineers… more
- SpaceX (Sunnyvale, CA)
- …drive execution + Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration ... (eg synthesis, floorplanning, power/ground grid generation, place and route, timing , noise, physical verification, electromigration, voltage drop, logic equivalency… more